Granted Patent B2

US 12,411,996 · App. 17/884,704 · Granted Sep 9, 2025

Inventors: Manoj Kumar (Yorktown Heights, NY); Silvia Melitta Mueller (St. Ingbert, DE); Debapriya Chatterjee (Austin, TX); Niels Fricke (Herrenberg, DE); Kattamuri Ekanadham (Mohegan Lake, NY); Maarten J. Boersma (Holzgerlingen, DE); Martijn Diede Berkers (Boeblingen, DE)

Assignee: International Business Machines Corporation

G06F21/72H04L9/0643H04L2209/12

Abstract

Claims (79)

1. A processor, comprising:

an instruction fetch unit that fetches instructions to be processed in the processor;

a register file including a plurality of registers for storing source operands and destination operands; and

an execution unit for executing a hash instruction obtained from the instructions, wherein the execution unit includes a hash circuit including at least:

a state register,

a state update circuit coupled to the state register,

a control circuit, and

a single instruction multiple data (SIMD) adder, wherein the SIMD adder is a dedicated component of the hash circuit,

wherein the execution unit, based on the hash instruction, is configured to perform:

receiving from the register file and buffering within the state register a current state of a message being hashed;

performing, in the state update circuit, a state update function on contents of the state register, wherein:

the state update function comprises a Secure Hash Algorthim 2 (SHA2) block hash function;

performing the state update function includes performing a plurality of iterative rounds of processing on contents of the state register and returning a result of each of the plurality of iterative rounds of processing to the state register; and

following completion of all of the plurality of iterative rounds of processing, adding, by the SIMD adder, contents of the state register to a current state of the message being hashed and storing a resulting sum to the register file as an updated state of the message.

2. The processor of claim 1 , wherein:

the state update function comprises a Secure Hash Algorithm 3 (SHA3) state permute function; and

performing a plurality of iterative rounds of processing includes performing twenty-four rounds of processing in which each round utilizes as an input a respective one of twenty-four round indices.

3. The processor of claim 1 , wherein

the state update function comprises a Secure Hash Algorithm 3 (SHA3) state permute function; and

performing a plurality of iterative rounds of processing includes performing a number of rounds of processing in indicated by the hash instruction.

4. The processor of claim 1 , wherein the execution unit executes the hash instruction in a squeezing phase of a Secure Hash Algorithm and Keccak (SHAKE) hash algorithm.

5. The processor of claim 1 , wherein:

the execution unit further includes a message block register for buffering a message block of the message and a message schedule round circuit coupled to the message block register; and

performing a state update function includes performing, by the message schedule round circuit, a plurality of iterative rounds of processing on contents of the message block register and returning a result of each of the plurality of iterative rounds of processing to the message block register.

6. The processor of claim 1 , wherein:

the state update circuit includes a data path for data words having a first data width; and

the execution unit is configured, based on the hash instruction indicating a second data width that is narrower than the first data width, to expand data words of a message block of the message to the first data width prior to processing the data words of the message in the state update circuit.

7. A method of data processing in a processor, said method comprising:

fetching, by an instruction fetch unit, instructions to be processed by the processor, wherein the instructions include a hash instruction; and

based on receiving the hash instruction, an execution unit of the processor executing the hash instruction, wherein the execution unit includes a hash circuit including:

at least a state register,

a state update circuit coupled to the state register,

a control circuit, and

a single instruction multiple data (SIMD) adder, wherein the SIMD adder is a distinct pipeline shared by the hash circuit and at least one other hash circuit,

wherein the executing includes:

receiving from a register file and buffering within the state register a current state of a message being hashed;

performing, in the state update circuit, a state update function on contents of the state register, wherein:

the state update function comprises a Secure Hash Algorthim 2 (SHA2) block hash function;

performing the state update function includes performing a plurality of iterative rounds of processing on contents of the state register and returning a result of each of the plurality of iterative rounds of processing to the state register; and

following completion of all of the plurality of iterative rounds of processing, adding, by the SIMD adder, contents of the state register to a current state of a message being hashed and storing a resulting sum to the register file as an updated state of the message.

8. The method of claim 7 , wherein:

the state update function comprises a Secure Hash Algorithm 3 (SHA3) state permute function; and

performing a plurality of iterative rounds of processing includes performing twenty-four rounds of processing in which each round utilizes as an input a respective one of twenty-four round indices.

9. The method of claim 7 , wherein executing the hash instruction includes executing the hash instruction in a squeezing phase of a Secure Hash Algorithm and Keccak (SHAKE) hash algorithm.

10. The method of claim 7 , wherein:

the execution unit further includes a message block register for buffering a message block of the message and a message schedule round circuit coupled to the message block register; and

performing a state update function includes performing a plurality of iterative rounds of processing on contents of the message block register in the message schedule round circuit and returning a result of each of the plurality of iterative rounds of processing to the message block register.

11. The method of claim 7 , wherein:

the state update circuit includes a data path for data words having a first data width; and

the method further comprises:

based on the hash instruction indicating a second data width that is narrower than the first data width, expanding data words of a message block of the message to the first data width prior to processing the data words of the message in the state update circuit.

12. A program product, comprising:

a machine-readable storage device; and

a design structure embodied in the machine-readable storage device, wherein the design structure is for designing, manufacturing, or testing an integrated circuit, the design structure including:

a processor, including:

an instruction fetch unit that fetches instructions to be executed;

a register file including a plurality of registers for storing source and destination operands;

and

an execution unit for executing a hash instruction obtained from the instructions, wherein the execution unit includes a hash circuit including at least:

a state register,

a state update circuit coupled to the state register,

a control circuit, and

a single instruction multiple data (SIMD) an adder, wherein the SIMD adder is a distinct pipeline shared by the hash circuit and at least one other hash circuit,

wherein the execution unit, based on the hash instruction, is configured to perform:

receiving from the register file and buffering within the state register a current state of a message being hashed;

performing, in the state update circuit, a state update function on contents of the state register, wherein:

the state update function comprises a Secure Hash Algorthim 2 (SHA2) block hash function;

performing the state update function includes performing a plurality of iterative rounds of processing on contents of the state register and returning a result of each of the plurality of iterative rounds of processing to the state register; and

following completion of all of the plurality of iterative rounds of processing, adding by the SIMD adder, contents of the state register to a current state of a message being hashed and storing a resulting sum to the register file as an updated state of the message.

13. The program product of claim 12 , wherein:

the state update function comprises a Secure Hash Algorithm 3 (SHA3) state permute function; and

performing a plurality of iterative rounds of processing includes performing twenty-four rounds of processing in which each round utilizes as an input a respective one of twenty-four round indices.

14. The program product of claim 12 , wherein the execution unit executes the hash instruction in a squeezing phase of a Secure Hash Algorithm and Keccak (SHAKE) hash algorithm.

15. The program product of claim 12 , wherein:

the execution unit further includes a message block register for buffering a message block of the message and a message schedule round circuit coupled to the message block register; and

performing a state update function includes performing, by the message schedule round circuit, a plurality of iterative rounds of processing on contents of the message block register and returning a result of each of the plurality of iterative rounds of processing to the message block register.

16. The program product of claim 12 , wherein:

the state update circuit includes a data path for data words having a first data width; and

the execution unit is configured, based on the hash instruction indicating a second data width that is narrower than the first data width, to expand data words of a message block of the message to the first data width prior to processing the data words of the message in the state update circuit.

Assignments (1)

Continuity (1)

References Cited (106)