System on chip having three-dimensional chiplet structure and electronic device including the system on chip
Provided are a system on chip (SoC) having a three-dimensional (3D) chiplet structure, and an electronic device including the SoC. The electronic device includes a printed circuit board, the SoC on the printed circuit board, and a memory device on the SoC, wherein the SoC includes an SoC package substrate, a first die arranged on the SoC package substrate, and having a logic circuit thereon, and a second die arranged on the first die, and having a logic circuit thereon.
1 . An electronic device comprising:
a printed circuit board;
a system on chip (SoC) on the printed circuit board; and
a memory device on the SoC;
an interconnection via; and
an interposer substrate between the SoC and the memory device, electrically connecting the SoC to the memory device,
wherein the SoC comprises
a SoC package substrate;
a first die on the SoC package substrate, and having a logic circuit thereon; and
a second die on the first die, and having a logic circuit thereon,
wherein the interconnection via vertically extends in a direction from a contact location with the first die within the SoC to an external surface of the SoC facing the memory device penetrating the interposer substrate, the contact location being outside an outermost perimeter of the second die.
2 . The electronic device of claim 1 ,
wherein the first die comprises a first substrate, and a first active layer on the first substrate and having a semiconductor element thereon,
the second die comprises a second substrate, and a second active layer on the second substrate and having a semiconductor element thereon, and
the first active layer and the second active layer are arranged face to face.
3 . The electronic device of claim 1 , wherein
the first die comprises a first substrate, and a first active layer on the first substrate and having a semiconductor element thereon,
the second die comprises a second substrate, and a second active layer on the second substrate and having a semiconductor element thereon,
the first active layer faces the SoC package substrate, and
the second active layer faces the first die.
4 . The electronic device of claim 1 ,
wherein a size of the first die is greater than a size of the second die.
5 . The electronic device of claim 1 ,
wherein a size of the second die is greater than a size of the first die.
6 . The electronic device of claim 1 ,
further comprising a voltage regulator configured to receive an input voltage and generate an output voltage to be used by the SoC,
wherein the voltage regulator is mounted on the SoC package substrate.
7 . The electronic device of claim 6 ,
wherein the voltage regulator is in parallel with the first die on a same flat surface.
8 . The electronic device of claim 1 ,
further comprising a voltage regulator configured to receive an input voltage and configured to generate an output voltage to be used by the SoC,
wherein the voltage regulator is on the first die.
9 . The electronic device of claim 1 ,
further comprising a voltage regulator configured to receive an input voltage and generate an output voltage to be used by the SoC,
wherein the voltage regulator is embedded in one of the first die and the second die.
10 . The electronic device of claim 1 , wherein
the SoC comprises a memory controller configured to
transmit a data input/output signal to the memory device, and
receive the data input/output signal from the memory device, and
a signal path electrically connecting the memory controller to the memory device and configured to transmit the data input/output signal, the signal path comprising the interconnection via.
11 . The electronic device of claim 1 , wherein
the SoC comprises a memory controller configured to transmit a data input/output signal to the memory device, and receive the data input/output signal from the memory device, and
a signal path electrically connecting the memory controller to the memory device and configured to transmit the data input/output signal, the signal path comprising the interconnection via.
12 . An electronic device comprising:
a printed circuit board;
a system on chip (SoC) on the printed circuit board, and comprising at least two logic die having a logic circuit thereon;
a memory device on the SoC;
an interposer substrate between the SoC and the memory device, and electrically connecting the SOC to the memory device; and
an interconnection via vertically extending in a direction from a contact location with one of the at least two logic die within the SoC to an external surface of the SoC facing the memory device to electrically connect the one of the at least two logic die to the memory device, penetrating the interposer substrate, the contact location being outside an outermost perimeter of another one of the at least two logic die.
13 . The electronic device of claim 12 , wherein
the at least two logic die comprises a plurality of vertically stacked logic dies, and
the interconnection via is vertically extending in a direction from a first die, which is lowermost of the plurality of vertically stacked logic dies, to the memory device.
14 . The electronic device of claim 12 , wherein
the at least two logic die comprises a plurality of vertically stacked logic dies, and
the interconnection via is vertically extending in a direction from a second die, which is uppermost of the plurality of vertically stacked logic dies, to the memory device.
15 . The electronic device of claim 12 ,
wherein the SoC further comprises a molding layer surrounding the at least two logic die, and
the interconnection via comprises a through mold via penetrating the molding layer.
16 . The electronic device of claim 12 ,
wherein the interconnection via comprises a through silicon via penetrating the interposer substrate.
17 . The electronic device of claim 12 ,
further comprising a voltage regulator configured to receive an input voltage and generate an output voltage to be used by the SoC,
wherein the voltage regulator is mounted on a SoC package substrate of the SoC, and in parallel with the at least two logic die on a same flat surface.
18 . The electronic device of claim 12 ,
further comprising a voltage regulator configured to receive an input voltage and generate an output voltage to be used by the SoC,
wherein the voltage regulator is embedded in the at least two logic die.
19 . A system on chip (SoC) having a three-dimensional (3D) chiplet structure, the SoC comprising:
an SoC package substrate;
a first die on the SoC package substrate using a first bump, and having a first logic circuit thereon;
a second die on the first die, and having a second logic circuit thereon; and
an interconnection via; and
interposer substrate on an external surface of the SoC, and electrically connected to the SoC,
wherein the first logic circuit and the second logic circuit receive an output voltage via an output voltage path, from a voltage regulator on the SoC package substrate,
a plurality of function blocks are on at least one of the first die and the second die, and
the interconnection via vertically extends in a direction from a contact location with the first die within the SoC to the external surface of the SoC opposite the SoC package substrate, penetrating the interposer substrate, the contact location being outside an outermost perimeter of the second die.