Embedded bridge substrate having an integral device
Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.
1. A microelectronic assembly, comprising:
a bridge embedded in a substrate,
the bridge having a bridge substrate layer at a first surface side and one or more routing layers at an opposing second surface side,
a first integral passive component in the bridge substrate layer,
a second integral passive component in the one or more routing layers,
a first die coupled to the first and second integral passive components via first and second contacts on the bridge,
a second die coupled to the first die via a first conductive pathway of the one more routing layers,
a third die coupled to the second die via a second conductive pathway directly embedded in a material of the substrate away from the bridge.
2. The microelectronic assembly of claim 1 , wherein the first or second integral passive component is a thin film resistor (TFR).
3. The microelectronic assembly of claim 2 , wherein the TFR is part of a calibration circuit.
4. The microelectronic assembly of claim 1 , wherein the first or second integral passive component is an array of capacitors.
5. The microelectronic assembly of claim 4 , wherein an individual capacitor in the array of capacitors is one of a trench capacitor, a metal-oxide-semiconductor (MOS) capacitor, a metal-insulator-metal (MIM) capacitor, or a parallel plate capacitor.
6. The microelectronic assembly of claim 4 , wherein the array of capacitors is part of an input/output circuit.
7. The microelectronic assembly of claim 1 , wherein the first integral passive component is a thin film transistor (TFR) and the second integral passive component is a capacitor.
8. The microelectronic assembly of claim 1 , wherein the second integral passive component is at the second surface of the bridge.
9. The microelectronic assembly of claim 1 , further comprising:
a third integral passive component in the one or more routing layers, and wherein the second die is coupled to the third integral passive component via a third contact on the bridge.
10. A computing device, comprising:
a circuit board; and
an integrated circuit (IC) package disposed on the circuit board, wherein the IC package includes:
a bridge embedded in a package substrate;
the bridge having a bridge substrate layer at a first surface side and one or more routing layers at an opposing second surface side,
a first thin film transistor (TFR) in the bridge substrate layer,
a second thin film transistor (TFR) in the one or more routing layers,
a first die coupled to the first and second TFRs via first and second contacts on the bridge,
a second die coupled to the first die via a first conductive pathway of the one more routing layers,
a third die coupled to the second die via a second conductive pathway directly embedded in a material of the substrate away from the bridge.
11. The computing device of claim 10 , wherein the first TFR is part of a calibration circuit.
12. The computing device of claim 10 , wherein the bridge further comprises:
a capacitor in the one or more routing layers.
13. The computing device of claim 10 , wherein the second TFR is one of a plurality of TFRs in the one or more routing layers.
14. An integrated circuit (IC) package, comprising:
a bridge embedded in a package substrate;
the bridge having a bridge substrate layer at a first surface side and one or more routing layers at an opposing second surface side,
a first capacitor in the bridge substrate layer,
a second capacitor in the one or more routing layers,
a first die coupled to the first and second capacitors via first and second contacts on the bridge,
a second die coupled to the first die via a first conductive pathway of the one more routing layers,
a third die coupled to the second die via a second conductive pathway directly embedded in a material of the substrate away from the bridge.
15. The IC package of claim 8 , further comprising:
a circuit board, wherein the third die is coupled to the circuit board via a third conductive pathway directly embedded in a material of the package substrate away from the bridge.
16. The IC package of claim 14 , wherein the first capacitor and the second capacitor are parallel plate capacitors.
17. The IC package of claim 14 , wherein the first capacitor and the second capacitor are part of an array of capacitors.