IP Library › Granted Patent US 12,482,681
Granted Patent B2
US 12,482,681 · App. 17/890,648 · Granted Nov 25, 2025

Semiconductor inspection method including heating a top surface of a semiconductor package

Inventors: Soonkyu Hwang (Asan-si, KR); Jinyeol Yang (Cheonan-si, KR); Haegu Lee (Anyang-si, KR); Jae-Min Jeon (Asan-si, KR); Jin Hee Han (Asan-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L21/67288G06T7/0004G06T2207/10048G06T2207/30148
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Quick Facts
Patent No.
US 12,482,681
App. No.
17/890,648
Granted
Nov 25, 2025
Kind
B2
Abstract

Disclosed are semiconductor inspection apparatuses, systems, and methods. The semiconductor inspection method comprises heating a top surface of a semiconductor package, capturing the top surface of the heated semiconductor package to obtain thermal image data, and analyzing the thermal image data. The analyzing the thermal image data includes analyzing first thermal image data about the top surface at a first region of the semiconductor package, and analyzing second thermal image data about the top surface at a second region of the semiconductor package. The analyzing the first thermal image data includes obtaining first region data about temperature distribution at the top surface of the first region, and using the first region data to obtain thickness data of a cover molding layer about thickness distribution of the molding layer on the chip in the first region.

Claims (51)

1 . A semiconductor inspection method, comprising:

heating a top surface of a semiconductor package to form a heated semiconductor package;

capturing the top surface of the heated semiconductor package to obtain thermal image data about the top surface of the semiconductor package; and

analyzing the thermal image data,

wherein analyzing the thermal image data includes,

analyzing first thermal image data about the top surface at a first region of the semiconductor package, the first region being provided with a chip, and

analyzing second thermal image data about the top surface at a second region of the semiconductor package, the second region being provided with no chip, and

wherein the analyzing the first thermal image data includes,

obtaining first region data about temperature distribution at the top surface of the first region, and

obtaining thickness data of a cover molding layer about a thickness distribution of a molding layer on the chip in the first region by using the first region data,

wherein the analyzing the second thermal image data includes:

obtaining second region data about a temperature distribution at the top surface of the second region; and

obtaining thickness data of a peripheral molding layer about a thickness distribution of the molding layer in the second region by using the second region data,

the method further comprising,

obtaining 3D shape data about an outward appearance of the semiconductor package by using a three-dimensional (3D) sensing device; and

analyzing the 3D shape data,

wherein the analyzing the 3D shape data includes using the 3D shape data to obtain 3D thickness data about the thickness distribution of the molding layer,

wherein the analyzing the second thermal image data further includes using the 3D thickness data to correct the thickness data of the peripheral molding layer, and

wherein the correcting the thickness data of the peripheral molding layer includes determining the 3D thickness data as a first value when the 3D thickness data is different from the thickness data of the peripheral molding layer obtained by using the second region data.

2 . The semiconductor inspection method of claim 1 , wherein the heating the top surface of the semiconductor package includes:

irradiating a linear laser beam on the top surface of the semiconductor package, the laser beam extending in a first direction; and

driving the semiconductor package to move in a second direction that intersects the first direction while the linear laser beam is irradiated on the semiconductor package.

3 . The semiconductor inspection method of claim 1 , further comprising:

generating a visual image of the semiconductor package; and

displaying the visual image on a display device by using the thickness data of the cover molding layer, the thickness data of the peripheral molding layer, and data of the chip.

4 . The semiconductor inspection method of claim 1 , wherein the analyzing the second thermal image data further includes:

determining whether one or more of a void, a crack, delamination, or foreign contamination is present on the molding layer by using the second region data.

5 . The semiconductor inspection method of claim 1 , wherein the obtaining the thickness data is based on a cubic polynomial relation between the thickness data, the first thermal image data, and the second thermal image data.

6 . The semiconductor inspection method of claim 1 , wherein a relation between the thickness distribution and a change in temperature is such that the change in temperature is greater than 4 Kelvins when a thickness of the cover molding layer is 100 um.

7 . A semiconductor inspection method, comprising:

obtaining 3D shape data about an outward appearance of a semiconductor package by using a three-dimensional (3D) sensing device;

heating a top surface of the semiconductor package;

capturing the top surface of the heated semiconductor package to obtain thermal image data about the top surface of the semiconductor package;

analyzing the 3D shape data; and

analyzing the thermal image data,

wherein analyzing the thermal image data includes,

analyzing first thermal image data about the top surface at a first region of the semiconductor package, the first region being provided with a chip; and

analyzing second thermal image data about the top surface at a second region of the semiconductor package, the second region being provided with no chip,

wherein the analyzing the second thermal image data includes:

obtaining second region data about temperature distribution at the top surface of the second region; and

obtaining thickness data of a peripheral molding layer in the second region by using the second region data,

wherein the analyzing the 3D shape data includes using the 3D shape data to obtain 3D thickness data in the semiconductor package, and

the analyzing the second thermal image data further includes correcting the thickness data of the peripheral molding layer by using the 3D thickness data to, and

wherein the correcting the thickness data of the peripheral molding layer includes determining the 3D thickness data as a first value when the 3D thickness data is different from the thickness data of the peripheral molding layer obtained by using the second region data.

8 . The semiconductor inspection method of claim 7 , wherein the analyzing the first thermal image data includes:

obtaining first region data about a temperature distribution at the top surface of the first region; and

obtaining thickness data of a cover molding layer on the chip in the first region by using the first region data.

9 . The semiconductor inspection method of claim 7 , further comprising:

changing a fabrication process of the semiconductor package based on the thickness data.

10 . The semiconductor inspection method of claim 7 , wherein the obtaining the thickness data is based on a cubic polynomial relation between the thickness data and the first thermal image data and the second thermal image data.

11 . The semiconductor inspection method of claim 7 , wherein a relation between a thickness of a cover molding layer and a change in temperature is such that the change in temperature is greater than 4 Kelvins when the thickness of the cover molding layer is 100 um.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2022
From: HWANG, SOONKYU; YANG, JINYEOL; LEE, HAEGU; JEON, JAE-MIN; HAN, JIN HEE
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 061234/0379 →
Priority Claims (1)
KR 10-2021-0182151 · Dec 17, 2021 · national
Continuity (1)
Related Publication 20230197485A1 · Jun 22, 2023
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