Granted Patent B2

US 12,322,654 · App. 17/893,218 · Granted Jun 3, 2025

Inventor: Yuanhao Gao (Hefei, CN)

Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.

H01L21/76898H01L21/7684H01L23/481H01L24/03H01L24/05H01L24/80H01L2224/0347H01L2224/05624H01L2224/05647H01L2224/05684H01L2224/80895H01L2224/80896

Abstract

Claims (36)

1. A method for forming a semiconductor structure, comprising:

providing a wafer in which a semiconductor device is formed;

forming a blind hole in the wafer;

depositing a first metal material in the blind hole to form a through silicon via;

removing the first metal material deposited on a surface of the wafer, and planarizing the surface of the wafer; and

forming a bonding pad on a planarized surface of the wafer;

wherein the forming a bonding pad on a planarized surface of the wafer comprises:

depositing a hard mask layer on the planarized surface of the wafer;

patterning the hard mask layer to form a via exposing the metal interconnection layer and the blind hole; and

depositing a second metal material in the via to form the bonding pad.

2. The method of claim 1 , wherein the providing a wafer in which a semiconductor device is formed comprises:

providing a substrate; and

forming the semiconductor device on the substrate, wherein the semiconductor device comprises a memory device and a metal interconnection layer.

3. The method of claim 1 , wherein a material of the hard mask layer material comprises silicon nitride.

4. The method of claim 1 , wherein the first metal material is same as the second metal material.

5. The method of claim 1 , wherein the blind hole is formed in the wafer by using at least one of a dry etching process or a wet etching process.

6. The method of claim 1 , wherein the depositing a first metal material in the blind hole to form a through silicon via comprises:

depositing an insulating layer covering an inner wall of the blind hole on the inner wall of the blind hole; and

depositing the first metal material to form a conductive layer of the through silicon via after the insulating layer is formed.

7. The method of claim 1 , wherein the planarizing the surface of the wafer comprises:

planarizing the surface of the wafer through a chemical mechanical grinding process.

8. The method of claim 1 , wherein a surface where the bonding pad is located is a first surface; and the method further comprises:

starting from a second surface opposite to the first surface, thinning the wafer on which the bonding pad is formed to a preset thickness.

9. A wafer on wafer bonding method, comprising:

providing a first wafer and a second wafer, wherein the first wafer and the second wafer are manufactured by the method of claim 1 ; and

performing wafer on wafer hybrid bonding on the first wafer and the second wafer.

10. A semiconductor structure, comprising:

a wafer in which a semiconductor device is formed;

a through silicon via formed in the wafer; and

a bonding pad electrically connected to the through silicon via;

wherein the semiconductor structure is formed with the method of claim 1 .

11. The semiconductor structure of claim 10 , wherein the wafer comprises:

a substrate; and

the semiconductor device formed on the substrate, wherein the semiconductor device comprises a memory device and a metal interconnection layer.

12. The semiconductor structure of claim 10 , wherein the through silicon via comprises an insulating layer and a conductive layer formed by using a first metal material; and

wherein the bonding pad is formed by using a second metal material.

Assignments (1)

Priority Claims (1)

Continuity (2)

References Cited (20)