IP Library Granted Patent US 12,635,336
Granted Patent B2
US 12,635,336 · App. 17/902,591 · Granted May 19, 2026

Display apparatus including first and second pixel circuits

Inventors: Pilsuk Lee (Yongin-si, KR); Yoomin Ko (Yongin-si, KR); Sunho Kim (Yongin-si, KR); Juchan Park (Yongin-si, KR)
Assignee: Samsung Display Co., Ltd.
H10K59/1213H10K59/131H10D86/421H10D86/441H10D86/60
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,635,336
App. No.
17/902,591
Granted
May 19, 2026
Kind
B2
Abstract

A display apparatus includes a substrate including a first display region and a second display region of a display region; a first pixel circuit disposed in the first display region and including a first semiconductor layer including a first channel region, a first gate electrode, and a first electrode; and a second pixel circuit disposed in the second display region and including a second semiconductor layer including a second channel region, a ratio of a first overlapping area of a first overlapping region of the first channel region overlapping the first electrode in a plan view to a first channel region of the first channel region is less than a ratio of a second overlapping area of a second overlapping region of the second channel region overlapping the second electrode to a second channel region of the second channel region in the plan view.

Claims (115)

1 . A display apparatus comprising:

a substrate comprising a first display region and a second display region of a display region;

a first pixel circuit disposed in the first display region and comprising:

a first semiconductor layer;

a first gate electrode; and

a first electrode, wherein

the first semiconductor layer comprises a first channel region, the first gate electrode overlaps the first channel region in a plan view, and the first electrode overlaps the first gate electrode in the plan view and is connected to the first gate electrode through a first contact hole formed in insulating layers interposed between the first electrode and the first gate electrode; and

a second pixel circuit disposed in the second display region and comprising:

a second semiconductor layer;

a second gate electrode; and

a second electrode, wherein

the second semiconductor layer comprises a second channel region, the second gate electrode overlaps the second channel region in the plan view, and the second electrode overlaps the second gate electrode in the plan view and is connected to the second gate electrode through a second contact hole formed in the insulating layers interposed between the second electrode and the second gate electrode,

wherein a ratio of a first overlapping area of a first overlapping region of the first channel region overlapping the first electrode to a first channel area of the first channel region in the plan view is less than a ratio of a second overlapping area of a second overlapping region of the second channel region overlapping the second electrode to a second channel area of the second channel region in the plan view, and

a ratio of a width of the second channel region to a length of the second channel region is greater than or equal to a ratio of a width of the first channel region to a length of the first channel region.

2 . The display apparatus of claim 1 , further comprising:

a gate driving circuit disposed in the second display region and transmits a gate signal to the first pixel circuit and the second pixel circuit, and

second display elements at least partially overlap the gate driving circuit in the plan view.

3 . The display apparatus of claim 1 , wherein

at least a portion of the first electrode overlaps the first channel region in the plan view.

4 . The display apparatus of claim 1 , wherein

a mobility of the second channel region is greater than a mobility of the first channel region.

5 . The display apparatus of claim 1 , wherein

an amount of hydrogen included in the second channel region is greater than an amount of hydrogen included in the first channel region.

6 . The display apparatus of claim 1 , wherein

each of the first electrode and the second electrode has a first layer and a second layer, the second layer being disposed on the first layer.

7 . The display apparatus of claim 1 , wherein

the first pixel circuit comprises:

a third semiconductor layer; and

a first connection electrode, the third semiconductor layer and the first semiconductor layer comprising a different material, and the first connection electrode electrically connecting the first electrode to the third semiconductor layer, and

the second pixel circuit comprises:

a fourth semiconductor layer; and

a second connection electrode, the fourth semiconductor layer and the second semiconductor layer comprising a different material, and the second connection electrode electrically connecting the second electrode to the fourth semiconductor layer.

8 . The display apparatus of claim 7 , wherein

each of the first semiconductor layer and the second semiconductor layer comprises a silicon semiconductor material, and

each of the third semiconductor layer and the fourth semiconductor layer comprises an oxide semiconductor material.

9 . The display apparatus of claim 8 , further comprising:

a data line disposed in the display region and extending in a first direction;

a data pad unit disposed outside of the display region; and

a connection line that transmits a data signal received from the data pad unit to the data line, and having a first portion and a second portion, the first portion extending in the first direction, and the second portion extending in a second direction and electrically connecting the first portion to the data line, wherein

the second portion of the connection line, the first connection electrode, and the second connection electrode are disposed on a same level.

10 . The display apparatus of claim 1 , wherein

the first pixel circuit comprises:

a third electrode;

a first conductive pattern; and

a third contact hole, and the third electrode is disposed between the first gate electrode and the first electrode, the first conductive pattern is disposed on the first electrode and receives a driving voltage, and the third contact hole connects the third electrode to the first conductive pattern,

the second pixel circuit comprises:

a fourth electrode;

a second conductive pattern; and

a fourth contact hole, wherein

the fourth electrode is disposed between the second gate electrode and the second electrode, the second conductive pattern is disposed on the second electrode and receives the driving voltage, and the fourth contact hole connects the fourth electrode to the second conductive pattern, and

a first distance between the third contact hole and the first channel region is less than a second distance between the fourth contact hole and the second channel region.

11 . The display apparatus of claim 1 , wherein

a peripheral region outside of the display region is included in the substrate, and

the second display region is disposed between the first display region and the peripheral region.

12 . A display apparatus comprising:

a substrate comprising a first display region and a second display region of a display region;

a first pixel circuit disposed in the first display region and comprising:

a first semiconductor layer;

a first gate electrode; and

a first electrode, wherein

the first semiconductor layer comprises a first channel region, the first gate electrode overlaps the first channel region in a plan view, and the first electrode overlaps the first gate electrode in the plan view and is connected to the first gate electrode through a first contact hole formed in insulating layers interposed between the first electrode and the first gate electrode;

a first display element disposed on the first display region and electrically connected to the first pixel circuit;

a second pixel circuit disposed in the second display region and comprising:

a second semiconductor layer;

a second gate electrode; and

a second electrode, wherein

the second semiconductor layer comprises a second channel region, the second gate electrode overlaps the second channel region in the plan view, and the second electrode overlaps the second gate electrode in the plan view and is connected to the second gate electrode through a second contact hole formed in the insulating layers interposed between the second electrode and the second gate electrode;

second display elements disposed on the second display region and electrically connected to the second pixel circuit,

wherein the first pixel circuit comprises a first driving transistor configured to output a first driving current to the first display element, and the second pixel circuit comprises a second driving transistor configured to output a second driving current to the second display elements,

wherein a ratio of a first overlapping area of a first overlapping region of the first channel region overlapping the first electrode to a first channel area of the first channel region in the plan view is less than a ratio of a second overlapping area of a second overlapping region of the second channel region overlapping the second electrode to a second channel area of the second channel region in the plan view, and

wherein a magnitude of the first driving current of the first display element that emits light with a first grayscale is less than a magnitude of the second driving current of the second display elements that emit light with the first grayscale.

13 . The display apparatus of claim 12 , wherein

the second driving current is equally distributed to the second display elements, and a magnitude of a current flowing in each of the second display elements is equal to a magnitude of the first driving current.

14 . The display apparatus of claim 12 , wherein

an emission area of each of the second display elements is equal to an emission area of the first display element.

15 . A display apparatus comprising:

a first pixel circuit comprising:

a first semiconductor layer;

a first gate electrode; and

a first electrode, wherein

the first semiconductor layer comprises a first channel region, the first gate electrode overlaps the first channel region in a plan view, and the first electrode overlaps the first gate electrode in the plan view and is connected to the first gate electrode through a first contact hole formed in insulating layers interposed between the first electrode and the first gate electrode;

a second pixel circuit comprising:

a second semiconductor layer;

a second gate electrode; and

a second electrode, wherein

the second semiconductor layer comprises a second channel region, the second gate electrode overlaps the second channel region in the plan view, and the second electrode overlaps on the second gate electrode in the plan view and is connected to the second gate electrode through a second contact hole formed in the insulating layers interposed between the second electrode and the second gate electrode;

a first display element electrically connected to the first pixel circuit; and

second display elements electrically connected to the second pixel circuit,

wherein a ratio of a first overlapping area of a first overlapping region of the first channel region overlapping the first electrode to a first channel area of the first channel region in the plan view is less than a ratio of a second overlapping area of a second overlapping region of the second channel region overlapping the second electrode to a second channel area of the second channel region in the plan view, wherein

the first pixel circuit further comprises:

a third electrode;

a first conductive pattern; and

a third contact hole, wherein

the third electrode is disposed between the first gate electrode and the first electrode, the first conductive pattern is disposed on the first electrode and receives a driving voltage, and the third contact hole connects the third electrode to the first conductive pattern,

the second pixel circuit further comprises:

a fourth electrode;

a second conductive pattern; and

a fourth contact hole, wherein

the fourth electrode is disposed between the second gate electrode and the second electrode, the second conductive pattern is disposed on the second electrode and receives the driving voltage, and the fourth contact hole connects the fourth electrode to the second conductive pattern, and

a first distance between the third contact hole and the first channel region is less than a second distance between the fourth contact hole and the second channel region.

16 . The display apparatus of claim 15 , wherein

the first pixel circuit comprises a first driving transistor having a portion of the first semiconductor layer and the first gate electrode and that outputs a first driving current to the first display element,

the second pixel circuit comprises a second driving transistor having a portion of the second semiconductor layer and the second gate electrode and outputs a second driving current to the second display elements, and

a number of the second display elements is n, and a magnitude of the second driving current is about n times a magnitude of the first driving current.

17 . The display apparatus of claim 15 , wherein

a ratio of a width of the second channel region to a length of the second channel region is greater than a ratio of a width of the first channel region to a length of the first channel region.

18 . The display apparatus of claim 15 , wherein

an amount of hydrogen included in the second channel region is greater than an amount of hydrogen included in the first channel region.

19 . The display apparatus of claim 15 , wherein

each of the first electrode and the second electrode has a first layer and a second layer, the second layer being disposed on the first layer.

20 . The display apparatus of claim 15 , wherein

the first pixel circuit comprises:

a third semiconductor layer; and

a first connection electrode, the third semiconductor layer comprising an oxide semiconductor material, and the first connection electrode electrically connecting the first electrode to the third semiconductor layer, and

the second pixel circuit comprises a fourth semiconductor layer and a second connection electrode, the fourth semiconductor layer comprising an oxide semiconductor material, and the second connection electrode electrically connecting the second electrode and the fourth semiconductor layer to each other.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 2, 2022
From: LEE, PILSUK; KO, YOOMIN; KIM, SUNHO; PARK, JUCHAN
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 060984/0454 →
Priority Claims (1)
KR 10-2022-0013611 · Jan 28, 2022 · national
Continuity (1)
Related Publication 20230247863A1 · Aug 3, 2023
References Cited (14)
US 8324618B2 · Udagawa · 2012 [cited by examiner]
US 9905557B2 · Saito · 2018 [cited by examiner]
US 10290745B2 · Yamazaki et al. · 2019 [cited by applicant]
US 10326026B2 · Yamazaki · 2019 [cited by applicant]
US 11107416B2 · Cho et al. · 2021 [cited by applicant]
US 11791345B2 · Takahata · 2023 [cited by examiner]
US 11968862B2 · Diao · 2024 [cited by examiner]
US 12284872B2 · Yuan · 2025 [cited by examiner]
US 20210202633A1 · Song et al. · 2021 [cited by applicant]
JP 2021101468 · 2021 [cited by applicant]
KR 1020060084216A · 2006 [cited by applicant]
KR 102109601 · 2020 [cited by applicant]
KR 1020200129222A · 2020 [cited by applicant]
KR 1020210084733 · 2021 [cited by applicant]