IP Library Granted Patent US 12,566,910
Granted Patent B2
US 12,566,910 · App. 17/932,538 · Granted Mar 3, 2026

Algorithmic circuit design automation

Inventors: Shun Zhang (San Mateo, CA); Xin Zhang (Chappaqua, NY); Shaoze Fan (East Newark, NJ); Ningyuan Cao (Countryside, IL); Jing Li (Clifton, NJ); Xiaoxiao Guo (Mountain View, CA); Chuang Gan (Cambridge, MA)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
G06F30/398G06F30/27G06F30/323G06F30/327G06F30/3308G06F30/337G06F30/367G06F30/373G06F2119/02
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,566,910
App. No.
17/932,538
Granted
Mar 3, 2026
Kind
B2
Abstract

A method, system, and computer program product for circuit design automation. The method identifies a set of circuit components for a proposed circuit design. A subset of circuit components is selected to generate an initial topology for the proposed circuit design. A set of subsequent topologies are iteratively generated by a heuristic search algorithm based on the subset of circuit components and the initial topology. A set of valid topologies of the set of subsequent topologies are determined by a circuit simulator based on the subset of circuit components and a set of connections within the set of subsequent topologies. The method generates the proposed circuit design from the set of valid topologies.

Claims (49)

1 . A computer-implemented method, comprising:

identifying a set of circuit components for a proposed circuit design;

selecting a subset of circuit components to generate an initial topology for the proposed circuit design;

iteratively generating, by a heuristic search algorithm, a set of subsequent topologies based on the subset of circuit components and the initial topology;

determining, by a circuit simulator, a set of valid topologies of the set of subsequent topologies based on the subset of circuit components and a set of connections within the set of subsequent topologies; and

generating the proposed circuit design from the set of valid topologies.

2 . The method of claim 1 , wherein iteratively generating the set of subsequent topologies further comprises:

sequentially adding circuit components of the subset of circuit components to the proposed circuit design; and

sequentially adding a set of component connections of the sequentially added circuit components of the proposed circuit design.

3 . The method of claim 2 , wherein the circuit components of the subset of circuit components and the set of component connections are sequentially added by a Markov decision process.

4 . The method of claim 3 , wherein the Markov decision process sequentially adds the circuit components of the subset of circuit components first, and the Markov decision process sequentially adds the set of component connections second, the set of component connections being added after the subset of circuit components have been added.

5 . The method of claim 2 , wherein the circuit components of the subset of circuit components and the set of component connections are sequentially added in a predetermined order.

6 . The method of claim 1 , wherein the heuristic search algorithm is a Monte Carlo tree search algorithm.

7 . The method of claim 6 , wherein iteratively generating the set of subsequent topologies further comprises:

generating a first subsequent topology based on the initial topology and the Monte Carlo tree search algorithm; and

generating a second subsequent topology based on the first subsequent topology and the Monte Carlo tree search algorithm.

8 . A system, comprising:

one or more processors; and

a computer-readable storage medium, coupled to the one or more processors, storing program instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:

identifying a set of circuit components for a proposed circuit design;

selecting a subset of circuit components to generate an initial topology for the proposed circuit design;

iteratively generating, by a heuristic search algorithm, a set of subsequent topologies based on the subset of circuit components and the initial topology;

determining, by a circuit simulator, a set of valid topologies of the set of subsequent topologies based on the subset of circuit components and a set of connections within the set of subsequent topologies; and

generating the proposed circuit design from the set of valid topologies.

9 . The system of claim 8 , wherein iteratively generating the set of subsequent topologies further comprises:

sequentially adding circuit components of the subset of circuit components to the proposed circuit design; and

sequentially adding a set of component connections of the sequentially added circuit components of the proposed circuit design.

10 . The system of claim 9 , wherein the circuit components of the subset of circuit components and the set of component connections are sequentially added by a Markov decision process.

11 . The system of claim 10 , wherein the Markov decision process sequentially adds the circuit components of the subset of circuit components first, and the Markov decision process sequentially adds the set of component connections second, the set of component connections being added after the subset of circuit components have been added.

12 . The system of claim 9 , wherein the circuit components of the subset of circuit components and the set of component connections are sequentially added in a predetermined order.

13 . The system of claim 8 , wherein the heuristic search algorithm is a Monte Carlo tree search algorithm.

14 . The system of claim 13 , wherein iteratively generating the set of subsequent topologies further comprises:

generating a first subsequent topology based on the initial topology and the Monte Carlo tree search algorithm; and

generating a second subsequent topology based on the first subsequent topology and the Monte Carlo tree search algorithm.

15 . A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions being executable by one or more processors to cause the one or more processors to perform operations comprising:

identifying a set of circuit components for a proposed circuit design;

selecting a subset of circuit components to generate an initial topology for the proposed circuit design;

iteratively generating, by a heuristic search algorithm, a set of subsequent topologies based on the subset of circuit components and the initial topology;

determining, by a circuit simulator, a set of valid topologies of the set of subsequent topologies based on the subset of circuit components and a set of connections within the set of subsequent topologies; and

generating the proposed circuit design from the set of valid topologies.

16 . The computer program product of claim 15 , wherein iteratively generating the set of subsequent topologies further comprises:

sequentially adding circuit components of the subset of circuit components to the proposed circuit design; and

sequentially adding a set of component connections of the sequentially added circuit components of the proposed circuit design.

17 . The computer program product of claim 16 , wherein the circuit components of the subset of circuit components and the set of component connections are sequentially added by a Markov decision process and wherein the Markov decision process sequentially adds the circuit components of the subset of circuit components first, and the Markov decision process sequentially adds the set of component connections second, the set of component connections being added after the subset of circuit components have been added.

18 . The computer program product of claim 16 , wherein the circuit components of the subset of circuit components and the set of component connections are sequentially added in a predetermined order.

19 . The computer program product of claim 15 , wherein the heuristic search algorithm is a Monte Carlo tree search algorithm.

20 . The computer program product of claim 19 , wherein iteratively generating the set of subsequent topologies further comprises:

generating a first subsequent topology based on the initial topology and the Monte Carlo tree search algorithm; and

generating a second subsequent topology based on the first subsequent topology and the Monte Carlo tree search algorithm.

Assignments (3)
CONFIRMATORY LICENSE Recorded Apr 24, 2023
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: U.S. DEPARTMENT OF ENERGY
Reel/Frame 063447/0194 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2022
From: ZHANG, XIN; FAN, SHAOZE; GUO, XIAOXIAO; GAN, CHUANG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 061110/0578 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2022
From: ZHANG, SHUN; CAO, NINGYUAN; LI, JING
To: NEW JERSEY INSTITUTE OF TECHNOLOGY
Reel/Frame 061111/0087 →
Continuity (1)
Related Publication 20240095435A1 · Mar 21, 2024
References Cited (38)
US 5084824A · Lam · 1992 [cited by applicant]
US 8473885B2 · Cohn · 2013 [cited by applicant]
US 9846753B2 · Lee · 2017 [cited by applicant]
US 10380297B2 · Sendig · 2019 [cited by applicant]
US 10409938B2 · Foreman · 2019 [cited by applicant]
US 10528644B1 · Zhang · 2020 [cited by applicant]
US 10678981B2 · Ankenapalli · 2020 [cited by examiner]
US 10706195B1 · Rezende Barbosa · 2020 [cited by examiner]
US 10776548B1 · Liu · 2020 [cited by applicant]
US 10872192B1 · Ginetti · 2020 [cited by examiner]
US 10909293B1 · Zhang · 2021 [cited by applicant]
US 11120358B2 · Horesh · 2021 [cited by applicant]
US 11126772B1 · Manna · 2021 [cited by examiner]
US 11132485B2 · Landman · 2021 [cited by applicant]
US 20020032894A1 · Miyazaki · 2002 [cited by examiner]
US 20030079188A1 · McConaghy · 2003 [cited by examiner]
US 20040103263A1 · Colavin · 2004 [cited by examiner]
US 20110154275A1 · Hambardzumyan · 2011 [cited by examiner]
US 20130139119A1 · Hidvegi · 2013 [cited by examiner]
US 20160232268A1 · Rajagopalan · 2016 [cited by examiner]
US 20190034563A1 · Ankenapalli · 2019 [cited by examiner]
US 20200090072A1 · Troyer · 2020 [cited by applicant]
US 20200151295A1 · Chen · 2020 [cited by applicant]
US 20200401925A1 · Hertzberg · 2020 [cited by applicant]
US 20210056468A1 · Cao · 2021 [cited by applicant]
US 20210278825A1 · Wen · 2021 [cited by applicant]
US 20210397770A1 · Bompard · 2021 [cited by examiner]
US 20220092240A1 · Chi · 2022 [cited by examiner]
CA 2408705A1 · 2003 [cited by examiner]
CA 2631559A1 · 2009 [cited by examiner]
WO WO9966432A1 · 1999 [cited by examiner]
WO WO2009151934A1 · 2009 [cited by examiner]
Awais, et al., “An MCTS-Based Framework for Synthesis of Approximate Circuits,” IEEE, 2018, pp. 219-224. [cited by applicant]
Meng et al.; “Advanced Ordering Search for Multi-Level Approximate Logic Synthesis”, IWLS 28th International Workshop, Jun. 21-23, 2019, 8 pages. [cited by applicant]
Mirhoseini, et al., “A graph placement methodology for fast chip design,” Nature, Jun. 10, 2021, 23 pages, vol. 594. [cited by applicant]
Sinha et al., “Qubit Routing Using Graph Neural Network Aided Monte Carlo Tree Search,” arXiv:2104.01992v1, Apr. 1, 2021, 10 pages. [cited by applicant]
Witschen qt al., “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,” Microelectronics Reliability, 2019, 14 pages. [cited by applicant]
Zhou et al., “Supervised Learning Enhanced Quantum Circuit Transformation,” arXiv:20110.03057v1, Oct. 6, 2021, 9 pages. [cited by applicant]