Methods for producing a 3D semiconductor memory device and structure
A method for producing a 3D memory device including: providing a first level including a first single-crystal layer and control circuits, where the first level includes at least two interconnecting metal layers; forming at least one second level disposed above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level; each of first memory cells include one first transistor and each of second memory cells include one second transistor, where first memory cells and second memory cells are a NAND nonvolatile type memory, and at least one of the second transistors include a metal gate.
1. A method for producing a 3D memory device, the method comprising:
providing a first level comprising a single-crystal layer and control circuits,
wherein said first level comprises at least two interconnecting metal layers;
forming at least one second level disposed above said first level;
performing a first etch step comprising etching holes within said at least one second level;
forming at least one third level disposed above said at least one second level;
performing a second etch step comprising etching holes within said third level; and
performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level,
wherein each of said first memory cells comprise one first transistor,
wherein each of said second memory cells comprise one second transistor,
wherein said control circuits comprise a plurality of third transistors,
wherein at least one of said first or second transistors has a channel, a source, and a drain each having a same doping type,
wherein said first etch step is directly followed by a first deposition of a tunneling dielectric and then a second deposition comprising polysilicon,
wherein said control circuits comprise memory peripheral circuits,
wherein at least one of said first memory cells is at least partially atop a portion of said memory peripheral circuits, and
wherein said first memory cells and said second memory cells are a NAND nonvolatile type memory.
2. The method according to claim 1 ,
wherein said processing steps to form said plurality of first memory cells comprise a gate replacement process.
3. The method according to claim 1 ,
wherein said third level comprises at least two overlying layers comprising different materials.
4. The method according to claim 1 ,
wherein said method of processing at least said memory peripheral circuits accounts for a thermal budget associated with processing said first transistors and with processing said second transistors by adjusting an annealing of said plurality of third transistors accordingly.
5. The method according to claim 1 , further comprising:
an etch step comprising formation of said first transistors and said second transistors,
wherein at least a portion of said second transistors are atop said first transistors.
6. The method according to claim 1 ,
wherein said first deposition or said second deposition comprises use of Atomic Layer Deposition (“ALD”).
7. The method according to claim 1 ,
wherein said first etch step comprises use of a Reactive Ion Etching (“RIE”) process.
8. A method for producing a 3D memory device, the method comprising:
providing a first level comprising a first single-crystal layer and control circuits,
wherein said first level comprises at least two interconnecting metal layers;
forming at least one second level disposed above said first level;
performing a first etch step comprising etching holes within said second level;
forming at least one third level above said at least one second level;
performing a second etch step comprising etching holes within said third level; and
performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level;
wherein each of said first memory cells comprise one first transistor,
wherein each of said second memory cells comprise one second transistor,
wherein said first memory cells and said second memory cells are a NAND nonvolatile type memory, and
wherein at least one of said second transistors comprise a metal gate.
9. The method according to claim 8 ,
wherein said control circuits comprise memory peripheral circuits, and
wherein said memory peripheral circuits comprise control of said first memory cells and said second memory cells.
10. The method according to claim 8 ,
wherein said third level comprises at least two overlying layers each comprising different materials, and
wherein said different materials each comprise a differing etch rate and are selectively etch-able with respect to each other.
11. The method according to claim 8 ,
wherein said method of processing at least said memory peripheral circuits accounts for a thermal budget associated with processing of said first transistors and said second transistors by adjusting an annealing of said plurality of third transistors accordingly.
12. The method according to claim 8 , further comprising:
an etch step comprising formation of said first transistors and said second transistors,
wherein at least a portion of said second transistors are atop said first transistors.
13. The method according to claim 8 ,
wherein said first deposition or said second deposition comprises use of Atomic Layer Deposition (“ALD”).
14. The method according to claim 8 ,
wherein said first etch step comprises use of Reactive Ion Etching (RIE) process.
15. A method for producing a 3D memory device, the method comprising:
providing a first level comprising a first single crystal layer and control circuits,
wherein said control level comprises at least two interconnecting metal layers;
forming at least one second level above said first level;
performing a first etch step comprising etching holes within said second level;
forming at least one third level above said at least one second level;
performing a second etch step comprising etching holes within said third level; and
performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level,
wherein each of said first memory cells comprise one first transistor,
wherein each of said second memory cells comprise one second transistor,
wherein said performing additional processing steps comprises performing Atomic Layer Deposition (“ALD”), and
wherein at least one of said first or second transistors has a channel, a source, and a drain having a same doping type.
16. The method according to claim 15 ,
wherein said control circuits comprise memory peripheral circuits, and
wherein said memory peripheral circuits comprise control of said first memory cells and said second memory cells.
17. The method according to claim 15 ,
wherein said first memory cells and said second memory cells are a NAND nonvolatile type memory.
18. The method according to claim 15 ,
wherein said second level comprises at least two overlying layers each comprising different materials, and
wherein said different materials each comprise a differing etch rate, and are selectively etch-able with respect to each other.
19. The method according to claim 15 , further comprising:
an etch step comprising the formation of said first transistors and said second transistors,
wherein at least a portion of said second transistors are atop said first transistors.
20. The method according to claim 15 ,
wherein at least one of said second transistors comprise a metal gate.