Liquid crystal display device and electronic device including the same
A driver circuit includes first to third transistors, a first circuit, and a second circuit. In the first transistor, a first terminal is electrically connected to a second wiring, a second terminal is electrically connected to a first wiring, and a gate is electrically connected to the second circuit and a first terminal of the third transistor. In the second transistor, a first terminal is electrically connected to the first wiring, a second terminal is electrically connected to a sixth wiring, a gate is electrically connected to the first circuit and a gate of the third transistor. A second terminal of the third transistor is electrically connected to the sixth wiring. The first circuit is electrically connected to a third wiring, a fourth wiring, a fifth wiring, and the sixth wiring. The second circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring.
1. A semiconductor device comprising:
a pixel portion comprising a first transistor; and
a driver circuit comprising second to eleventh transistors,
wherein the pixel portion is electrically connected to the driver circuit through a first wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a clock signal line,
wherein one of a source and a drain of the third transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a power supply line,
wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the power supply line,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the third transistor and a gate of the fourth transistor through a first conductive layer,
wherein the first conductive layer is positioned in a same layer as a pixel electrode,
wherein the first conductive layer and the pixel electrode comprise a same material,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a first signal line,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the third transistor and the gate of the fourth transistor through the first conductive layer,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the power supply line,
wherein a gate of the sixth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to a gate of the fifth transistor through a second conductive layer,
wherein the second conductive layer is positioned in the same layer as the pixel electrode,
wherein the second conductive layer and the pixel electrode comprise the same material,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the first signal line,
wherein a gate of the seventh transistor is electrically connected to the first signal line,
wherein one of a source and a drain of the eighth transistor is electrically connected to the gate of the fifth transistor through the second conductive layer,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the power supply line,
wherein a gate of the eighth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the ninth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the ninth transistor is electrically connected to the power supply line,
wherein a gate of the ninth transistor is electrically connected to a second signal line,
wherein one of a source and a drain of the tenth transistor is electrically connected to the gate of the second transistor through a third conductive layer,
wherein the third conductive layer is positioned in the same layer as the pixel electrode,
wherein the third conductive layer and the pixel electrode comprise the same material,
wherein a gate of the tenth transistor is electrically connected to the second signal line,
wherein one of a source and a drain of the eleventh transistor is electrically connected to the gate of the second transistor, and
wherein the other of the source and the drain of the eleventh transistor is electrically connected to a third signal line.
2. A semiconductor device comprising:
a pixel portion comprising a first transistor; and
a driver circuit comprising second to eleventh transistors,
wherein the pixel portion is electrically connected to the driver circuit through a first wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a clock signal line,
wherein one of a source and a drain of the third transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a power supply line,
wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the power supply line,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the third transistor and a gate of the fourth transistor through a first conductive layer,
wherein the first conductive layer is positioned in a same layer as a pixel electrode,
wherein the first conductive layer and the pixel electrode comprise a same material,
wherein the other of the source and the drain of the fifth transistor is electrically connected to a first signal line,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the third transistor and the gate of the fourth transistor through the first conductive layer,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the power supply line,
wherein a gate of the sixth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to a gate of the fifth transistor through a second conductive layer,
wherein the second conductive layer is positioned in the same layer as the pixel electrode,
wherein the second conductive layer and the pixel electrode comprise the same material,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the first signal line,
wherein a gate of the seventh transistor is electrically connected to the first signal line,
wherein one of a source and a drain of the eighth transistor is electrically connected to the gate of the fifth transistor through the second conductive layer,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the power supply line,
wherein a gate of the eighth transistor is electrically connected to the gate of the second transistor,
wherein one of a source and a drain of the ninth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the ninth transistor is electrically connected to the power supply line,
wherein a gate of the ninth transistor is electrically connected to a second signal line,
wherein one of a source and a drain of the tenth transistor is electrically connected to the gate of the second transistor through a third conductive layer,
wherein the third conductive layer is positioned in the same layer as the pixel electrode,
wherein the third conductive layer and the pixel electrode comprise the same material,
wherein a gate of the tenth transistor is electrically connected to the second signal line,
wherein one of a source and a drain of the eleventh transistor is electrically connected to the gate of the second transistor,
wherein the other of the source and the drain of the eleventh transistor is electrically connected to a third signal line,
wherein in the second transistor, an area where the one of a source electrode and a drain electrode overlaps with a gate electrode is larger than an area where the other of the source electrode and the drain electrode overlaps with the gate electrode,
wherein in the fifth transistor, an area where the one of a source electrode and a drain electrode overlaps with a gate electrode is larger than an area where the other of the source electrode and the drain electrode overlaps with the gate electrode, and
wherein in the ninth transistor, an area where the one of a source electrode and a drain electrode overlaps with a gate electrode is larger than an area where the other of the source electrode and the drain electrode overlaps with the gate electrode.