Semiconductor device and electronic device
A data semiconductor device with a long retention time is provided. The semiconductor device includes a first transistor, a second transistor, a ferroelectric capacitor, a first capacitor, and a memory cell. Note that the memory cell includes a third transistor. A first gate of the first transistor is electrically connected to a first terminal of the ferroelectric capacitor, and a first terminal of the first transistor is electrically connected to a second gate of the first transistor and a first terminal of the second transistor. A second terminal of the second transistor is electrically connected to a second terminal of the ferroelectric capacitor and a first terminal of the first capacitor. A back gate of the third transistor is electrically connected to the first terminal of the first transistor. In the above structure, the threshold voltage of the third transistor can be increased by supplying a negative potential to the first terminal of the first transistor.
1. A semiconductor device comprising:
a first transistor, a second transistor, a ferroelectric capacitor, and a first capacitor,
wherein a first gate of the first transistor is electrically connected to a first terminal of the ferroelectric capacitor,
wherein a first terminal of the first transistor is electrically connected to a second gate of the first transistor and a first terminal of the second transistor, and
wherein a second terminal of the second transistor is electrically connected to a second terminal of the ferroelectric capacitor and a first terminal of the first capacitor.
2. The semiconductor device according to claim 1 ,
wherein the ferroelectric capacitor comprises a dielectric, and
wherein the dielectric comprises at least one of hafnium oxide and zirconium oxide.
3. The semiconductor device according to claim 1 , further comprising a second capacitor,
wherein a first terminal of the second capacitor is electrically connected to the first terminal of the first transistor and the first terminal of the second transistor.
4. The semiconductor device according to claim 1 ,
wherein a first gate of the second transistor is electrically connected to a second gate of the second transistor,
wherein the first gate of the second transistor is one of a front gate and a back gate of the second transistor, and
wherein the second gate of the second transistor is the other of the front gate and the back gate of the second transistor.
5. The semiconductor device according to claim 1 , further comprising a memory cell comprising a third transistor,
wherein one of a first gate and a second gate of the third transistor is electrically connected to the first terminal of the first transistor.
6. The semiconductor device according to claim 1 ,
wherein the first gate of the first transistor is one of a front gate and a back gate of the first transistor, and
wherein the second gate of the first transistor is the other of the front gate and the back gate of the first transistor.
7. A semiconductor device comprising:
a first transistor, a second transistor, a first ferroelectric capacitor, and a second ferroelectric capacitor,
wherein a first gate of the first transistor is electrically connected to a first terminal of the first ferroelectric capacitor,
wherein a first terminal of the first transistor is electrically connected to a second gate of the first transistor and a first terminal of the second transistor, and
wherein a second terminal of the second transistor is electrically connected to a second terminal of the first ferroelectric capacitor and a first terminal of the second ferroelectric capacitor.
8. The semiconductor device according to claim 7 ,
wherein each of the first ferroelectric capacitor and the second ferroelectric capacitor comprises a dielectric, and
wherein the dielectric of each of the first ferroelectric capacitor and the second ferroelectric capacitor comprises at least one of hafnium oxide and zirconium oxide.
9. The semiconductor device according to claim 7 , further comprising a second capacitor,
wherein a first terminal of the second capacitor is electrically connected to the first terminal of the first transistor and the first terminal of the second transistor.
10. The semiconductor device according to claim 7 ,
wherein a first gate of the second transistor is electrically connected to a second gate of the second transistor,
wherein the first gate of the second transistor is one of a front gate and a back gate of the second transistor, and
wherein the second gate of the second transistor is the other of the front gate and the back gate of the second transistor.
11. The semiconductor device according to claim 7 , further comprising a memory cell comprising a third transistor,
wherein one of a first gate and a second gate of the third transistor is electrically connected to the first terminal of the first transistor.
12. The semiconductor device according to claim 7 ,
wherein the first gate of the first transistor is one of a front gate and a back gate of the first transistor, and
wherein the second gate of the first transistor is the other of the front gate and the back gate of the first transistor.