IP Library Granted Patent US 12,628,330
Granted Patent B2
US 12,628,330 · App. 18/072,885 · Granted May 12, 2026

Semiconductor device

Inventors: Junhyeok Ahn (Suwon-si, KR); Hyosub Kim (Seoul, KR); Sohyun Park (Seoul, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10B12/30
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Quick Facts
Patent No.
US 12,628,330
App. No.
18/072,885
Granted
May 12, 2026
Kind
B2
Abstract

A semiconductor device includes a substrate having an active area and a non-active area. An extra pad layer is disposed on the active area of the substrate. A first contact layer is disposed in a contact hole defined inside the substrate from a surface of the extra pad layer. A first silicide layer is disposed on both sidewalls of the first contact layer. A buried insulating layer is buried in the contact hole at lateral sides of the first contact layer and the first silicide layer. A second silicide layer is disposed on an upper surface and sidewalls of the extra pad layer. A second contact layer is on the buried insulating layer and the second silicide layer and is in direct contact with the second silicide layer.

Claims (54)

1 . A semiconductor device comprising:

a substrate having an active area and a non-active area;

an extra pad layer disposed on the active area of the substrate;

a first contact layer disposed in a contact hole defined inside the substrate from a surface of the extra pad layer;

a first silicide layer disposed on both sidewalls of the first contact layer;

a buried insulating layer buried in the contact hole at lateral sides of the first contact layer and the first silicide layer;

a second silicide layer disposed on an upper surface and sidewalk of the extra pad layer; and

a second contact layer on the buried insulating layer and the second silicide layer and in direct contact with the second silicide layer.

2 . The semiconductor device of claim 1 , wherein the first contact layer and the first silicide layer are first contact plugs in contact with the active area of the substrate.

3 . The semiconductor device of claim 1 , wherein the first contact layer comprises a protrusion part protruding from the upper surface of the extra pad layer.

4 . The semiconductor device of claim 1 , wherein the second silicide layer is disposed on an entirety of the upper surface and sidewalls of the extra pad layer.

5 . The semiconductor device of claim 1 , wherein the second silicide layer is disposed inside a portion of the upper surface of the extra pad layer, and is disposed on an entirety of the sidewalls of the extra pad layer.

6 . The semiconductor device of claim 1 , wherein the first silicide layer is composed of a same material as the second silicide layer.

7 . The semiconductor device of claim 1 , wherein:

a recess hole exposing the second silicide layer is further defined on an upper surface of the buried insulating layer; and

the second contact layer is buried in the recess hole.

8 . The semiconductor device of claim 1 , wherein the buried insulating layer comprises a liner layer in direct contact with the first silicide layer and the second silicide layer in the contact hole, and a liner buried layer filling the contact hole on the liner layer.

9 . The semiconductor device of claim 1 , wherein the second contact layer is a second contact plug contacting the active area of the substrate through the second silicide layer and the extra pad layer.

10 . A semiconductor device comprising:

a substrate having an active area and a non-active area;

an extra pad layer disposed on the active area of the substrate;

a first contact silicide layer disposed in a contact hole defined inside the substrate from a surface of the extra pad layer;

a buried insulating layer buried in the contact hole on lateral sides of the first contact silicide layer;

a second silicide layer disposed on an upper surface and sidewalls of the extra pad layer; and

a second contact layer on the buried insulating layer and the second silicide layer and in direct contact with the second silicide layer.

11 . The semiconductor device of claim 10 , wherein:

the first contact silicide layer is a first contact plug in contact with the active area of the substrate; and

the second contact layer is a second contact plug contacting the active area of the substrate through the second silicide layer and the extra pad layer.

12 . The semiconductor device of claim 10 , wherein the first contact silicide layer is composed of a metal silicide layer.

13 . The semiconductor device of claim 10 , wherein the first contact silicide layer is composed of a same material as the second silicide layer.

14 . The semiconductor device of claim 10 , wherein the first contact silicide layer comprises a protrusion part protruding from the upper surface of the extra pad layer.

15 . The semiconductor device of claim 10 , wherein the second silicide layer is disposed inside a portion of the upper surface of the extra pad layer, and is disposed on an entirety of the sidewalls of the extra pad layer.

16 . A semiconductor device comprising:

a substrate having an active area and a non-active area;

an extra pad layer disposed on the active area of the substrate;

a pad isolation insulating layer disposed on the non-active area of the substrate and insulating the extra pad layer;

a first contact layer disposed in a contact hole defined inside the substrate from a surface of the extra pad layer;

a first silicide layer disposed on both sidewalls of the first contact layer;

a first conductive layer disposed on the first contact layer and the first silicide layer;

a buried insulating layer buried in the contact hole at lateral sides of the first contact layer and the first silicide layer;

a second silicide layer disposed on an upper surface and sidewalls of the extra pad layer;

a second contact layer on the buried insulating layer and the second silicide layer and in direct contact with the second silicide layer; and

a second conductive layer disposed on the pad isolation insulating layer and insulated from the second contact layer.

17 . The semiconductor device of claim 16 , wherein the first contact layer extends in a direction perpendicular to a surface of the substrate and comprises a protrusion part protruding from the upper surface of the extra pad layer.

18 . The semiconductor device of claim 16 , wherein:

an upper width of the first contact layer is less than a width of the first conductive layer; and

the upper width of the first silicide layer is equal to the width of the first conductive laver.

19 . The semiconductor device of claim 16 , wherein:

a buffer insulating layer is further disposed on the pad isolation insulating layer; and

the second conductive layer is disposed on the buffer insulating layer.

20 . The semiconductor device of claim 16 , wherein:

the first conductive layer and the second conductive layer are a first conductive line and a second conductive line extending in a first direction on the substrate, respectively;

the first contact layer and the first silicide layer are disposed under the first conductive line; and

the second contact layer is disposed between the first conductive line and the second conductive line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2022
From: AHN, JUNHYEOK; KIM, HYOSUB; PARK, SOHYUN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 061940/0188 →
Priority Claims (1)
KR 10-2022-0008690 · Jan 20, 2022 · national
Continuity (1)
Related Publication 20230247822A1 · Aug 3, 2023
References Cited (29)
US 4974055A · Haskell · 1990 [cited by examiner]
US 7611956B2 · Kim et al. · 2009 [cited by applicant]
US 8048737B2 · Kim et al. · 2011 [cited by applicant]
US 8148260B2 · Shin · 2012 [cited by applicant]
US 9024371B2 · Lee et al. · 2015 [cited by applicant]
US 9214382B2 · Lee et al. · 2015 [cited by applicant]
US 9368356B2 · Kim · 2016 [cited by applicant]
US 9601588B2 · Kim · 2017 [cited by applicant]
US 9640426B2 · Rho et al. · 2017 [cited by applicant]
US 10672773B2 · Ji et al. · 2020 [cited by applicant]
US 11037930B2 · Park et al. · 2021 [cited by applicant]
US 20140110851A1 · Kim · 2014 [cited by examiner]
US 20150364334A1 · Kang · 2015 [cited by examiner]
US 20150380508A1 · Kim · 2015 [cited by examiner]
US 20180211961A1 · Lin et al. · 2018 [cited by applicant]
US 20180331197A1 · Yamamoto · 2018 [cited by examiner]
US 20190131307A1 · Kim · 2019 [cited by examiner]
US 20190131421A1 · Shen · 2019 [cited by examiner]
US 20200343350A1 · Lee · 2020 [cited by examiner]
US 20200365537A1 · Choi · 2020 [cited by examiner]
US 20210057339A1 · Lee et al. · 2021 [cited by applicant]
US 20210098583A1 · Tsai · 2021 [cited by examiner]
US 20230260905A1 · Fang · 2023 [cited by examiner]
CN 105374820 · 2016 [cited by applicant]
KR 1020090034171A · 2009 [cited by applicant]
KR 1020150027363A · 2015 [cited by applicant]
KR 1020190112443A · 2019 [cited by applicant]
Office Action issued in corresponding TW Patent Application No. 112101921 on Dec. 12, 2023. [cited by applicant]
Office Action of Korean Patent Office in Application No. 10-2022-0008690, dated Jul. 14, 2025. [cited by applicant]