IP Library Granted Patent US 12,635,313
Granted Patent B2
US 12,635,313 · App. 18/084,186 · Granted May 19, 2026

Transfer method of aligning, placing, and bonding micro semiconductor chips on substrate

Inventors: Hyunjoon Kim (Suwon-si, KR); Seogwoo Hong (Suwon-si, KR); Dongkyun Kim (Suwon-si, KR); Dongho Kim (Suwon-si, KR); Joonyong Park (Suwon-si, KR); Sanghoon Song (Suwon-si, KR); Kyungwook Hwang (Suwon-si, KR); Junsik Hwang (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10H20/8506H10H20/857H10W90/00H10H20/0364
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Quick Facts
Patent No.
US 12,635,313
App. No.
18/084,186
Granted
May 19, 2026
Kind
B2
Abstract

Disclosed are a method of transferring semiconductor chips. The method may include providing a first substrate, adhering a support substrate to the first substrate, supplying and aligning a plurality of semiconductor chips, partially adhering a second substrate to a first surface of the first substrate, separating the support substrate from the first substrate, and adhering the plurality of semiconductor chips to the second substrate by supplying a fluid to a periphery of a second surface of the first substrate and applying a pressure to the second surface.

Claims (35)

1 . A method of transferring a semiconductor chip, the method comprising:

providing a first substrate having a first surface provided with a plurality of grooves and a second surface opposite to the first surface;

adhering a support substrate having a higher rigidity than the first substrate to the second surface of the first substrate;

supplying and aligning a plurality of semiconductor chips respectively to the plurality of grooves of the first substrate;

disposing a second substrate to face the first surface of the first substrate and partially adhering the second substrate to the first substrate;

separating the support substrate from the first substrate; and

adhering the plurality of semiconductor chips to the second substrate by supplying a fluid to a periphery of the second surface and applying a pressure to the second surface.

2 . The method of claim 1 , wherein the first substrate comprises a base film having a material less rigid than that of the support substrate and a pattern layer disposed on the base film and having a pattern corresponding to the plurality of grooves.

3 . The method of claim 2 , wherein the base film comprises at least one of polyethylene terephthalate (PET) and polyimide (PI).

4 . The method of claim 2 , wherein the providing of the first substrate comprises:

forming a polymer layer on one surface of the base film; and

forming the pattern corresponding to the plurality of grooves on the polymer layer.

5 . The method of claim 4 , wherein the plurality of grooves are formed in the polymer layer of the first substrate through an imprinting process.

6 . The method of claim 1 , wherein:

the support substrate is adhered to the second surface of the first substrate by using an adhesive layer, and

the support substrate is separated from the first substrate by weakening adhesive force of the adhesive layer.

7 . The method of claim 1 , wherein the second substrate is adhered to the first substrate by solder balls arranged in regions between the first substrate and the second substrate.

8 . The method of claim 7 , wherein the solder balls are partially arranged in edge regions between the first substrate and the second substrate.

9 . The method of claim 7 , further comprising, after the adhering of the plurality of semiconductor chips to the second substrate, separating the first substrate adhered to the second substrate from the second substrate by weakening an adhering strength of the solder balls.

10 . The method of claim 1 , further comprising, before the separating of the support substrate from the first substrate, turning upside down an assembly in which the first substrate, the second substrate, and the support substrate are connected to one another, such that the support substrate faces upward.

11 . The method of claim 1 , wherein the supplying and aligning of the plurality of semiconductor chips are performed according to a fluid self-assembly method.

12 . The method of claim 11 , wherein the fluid self-assembly method comprises:

supplying a liquid to the plurality of grooves; and

aligning the plurality of semiconductor chips with the plurality of grooves by scanning the first substrate by using an absorbing member capable of absorbing the liquid.

13 . The method of claim 11 , wherein the supplying and aligning of the plurality of semiconductor chips to the plurality of grooves further comprise arranging the plurality of semiconductor chips, such that electrodes of each of the plurality of semiconductor chips face upward.

14 . The method of claim 1 , wherein a curve is formed on the second surface of the first substrate according to a structure between the second substrate and the first substrate due to the pressure applied to the second surface.

15 . The method of claim 14 , wherein heights of some of the plurality of semiconductor chips are different from heights of other semiconductor chips of the plurality of semiconductor chips, or depths of some of the plurality of grooves are different from depths of other grooves of the plurality of grooves.

16 . The method of claim 14 , wherein a gas is supplied at a preset pressure into a chamber in which the first substrate and the second substrate partially adhered to each other are placed,

wherein the first substrate is pressed in a direction toward the second substrate by the gas supplied into the chamber, and

wherein the plurality of semiconductor chips are in contact with and are pressed against the second substrate.

17 . The method of claim 16 , wherein the adhering of the plurality of semiconductor chips to the second substrate further comprises heating the plurality of semiconductor chips to be adherable to the second substrate.

18 . The method of claim 1 , wherein:

the second substrate comprises a driving circuit board comprising a thin-film transistor, and

the second substrate and the plurality of semiconductor chips are adhered to and electrically connected to each other.

19 . The method of claim 1 , wherein the plurality of semiconductor chips comprise at least one of a light-emitting device and a memory chip.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2022
From: KIM, HYUNJOON; HONG, SEOGWOO; KIM, DONGKYUN; KIM, DONGHO; PARK, JOONYONG; SONG, SANGHOON; HWANG, KYUNGWOOK; HWANG, JUNSIK
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 062170/0380 →
Priority Claims (1)
KR 10-2022-0080856 · Jun 30, 2022 · national
Continuity (1)
Related Publication 20240006563A1 · Jan 4, 2024
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