IP Library › Granted Patent US 12,666,706
Granted Patent B2
US 12,666,706 · App. 18/094,452 · Granted Jun 23, 2026

Semiconductor device

Inventors: Su Young Bae (Suwon-si, KR); Jae Yeol Song (Suwon-si, KR); Oh Seong Kwon (Suwon-si, KR); Sang Yong Kim (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H10D84/85H10D30/014H10D30/43H10D30/6735H10D30/6739H10D62/121H10D64/017H10D84/0167H10D84/0181H10D84/038
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Quick Facts
Patent No.
US 12,666,706
App. No.
18/094,452
Filed
Jan 9, 2023
Granted
Jun 23, 2026
Kind
B2
Art Unit
2898
USPC
257/351
Abstract

A semiconductor device includes a substrate, an active pattern disposed on the substrate and extending in a first horizontal direction, a gate spacer disposed along each of sidewalls of a gate trench on the active pattern and extending in a second horizontal direction different from the first horizontal direction, a first gate insulating layer disposed along a sidewall and a bottom surface of the gate trench, a first conductive layer disposed on the first gate insulating layer inside the gate trench, a second gate insulating layer disposed on the first conductive layer inside the gate trench, and including a material different from a material of the first gate insulating layer, a second conductive layer disposed on the second gate insulating layer inside the gate trench, and a third conductive layer disposed on the second conductive layer so as to fill a remaining inner space of the gate trench.

Claims (26)

1 . A semiconductor device comprising:

a substrate;

an active pattern disposed on the substrate and extending in a first horizontal direction;

a gate spacer disposed along each of sidewalls of a gate trench on the active pattern and extending in a second horizontal direction different from the first horizontal direction;

a first gate insulating layer disposed along a sidewall and a bottom surface of the gate trench;

a first conductive layer disposed on the first gate insulating layer inside the gate trench;

a second gate insulating layer disposed on the first conductive layer inside the gate trench, and including a material different from a material of the first gate insulating layer;

a second conductive layer disposed on the second gate insulating layer inside the gate trench; and

a third conductive layer disposed on the second conductive layer so as to fill a remaining inner space of the gate trench,

wherein the uppermost surface of the first conductive layer is lower than the uppermost surface of the first gate insulating layer, and

wherein the second gate insulating layer disposed on the uppermost surface of the first conductive layer is in contact with the first gate insulating layer.

2 . The semiconductor device of claim 1 , further comprising a fourth conductive layer:

disposed between the second gate insulating layer and the second conductive layer,

in contact with each of the second gate insulating layer and the second conductive layer, and

including the same material as a material of the first conductive layer.

3 . The semiconductor device of claim 1 , wherein the second conductive layer is in contact with the second gate insulating layer.

4 . The semiconductor device of claim 1 , wherein a second dielectric constant of the second gate insulating layer is smaller than a first dielectric constant of the first gate insulating layer.

5 . The semiconductor device of claim 1 , wherein a thickness of the first gate insulating layer is greater than a thickness of the second gate insulating layer.

6 . The semiconductor device of claim 1 , wherein a thickness of the first gate insulating layer and a thickness of the second gate insulating layer are equal to each other.

7 . The semiconductor device of claim 1 , further comprising a plurality of nanosheets:

disposed on the active pattern,

stacked and spaced apart from each other in a vertical direction, and

surrounded the first conductive layer.

8 . The semiconductor device of claim 7 , wherein the first conductive layer is disposed on the first gate insulating layer so as to fill an entirety of a space between adjacent ones of the plurality of nanosheets.

9 . The semiconductor device of claim 7 , wherein the second gate insulating layer is disposed on the first conductive layer and between adjacent ones of the plurality of nanosheets.

10 . The semiconductor device of claim 9 , wherein the second conductive layer is disposed on the second gate insulating layer between adjacent ones of the plurality of nanosheets.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2023
From: BAE, SU YOUNG; SONG, JAE YEOL; KWON, OH SEONG; KIM, SANG YONG
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 062851/0253 →
Priority Claims (1)
KR 10-2022-0066605 · May 31, 2022 · national
Continuity (1)
Related Publication 20230387118A1 · Nov 30, 2023
References Cited (16)
US 10700064B1 · Zhang et al. · 2020 [cited by applicant]
US 11183431B2 · Savant et al. · 2021 [cited by applicant]
US 20170213826A1 · Kim · 2017 [cited by examiner]
US 20180069006A1 · Kim et al. · 2018 [cited by applicant]
US 20180197786A1 · Li · 2018 [cited by examiner]
US 20200381535A1 · Chang · 2020 [cited by examiner]
US 20210020631A1 · Park et al. · 2021 [cited by applicant]
US 20210098301A1 · Wu et al. · 2021 [cited by applicant]
US 20210134951A1 · Chen · 2021 [cited by examiner]
US 20210257263A1 · More et al. · 2021 [cited by applicant]
US 20210328035A1 · Kim et al. · 2021 [cited by applicant]
US 20210343705A1 · Chang et al. · 2021 [cited by applicant]
US 20210384313A1 · Cheng · 2021 [cited by applicant]
US 20210399104A1 · Chang et al. · 2021 [cited by applicant]
US 20220085006A1 · Kim · 2022 [cited by applicant]
KR 1020160095399A · 2016 [cited by applicant]