Semiconductor device including semiconductor chips stacked in a multi-layer structure by a flip-chip bonding method
A semiconductor device includes: a first semiconductor chip having an upper surface divided into a pixel array region and a connection region, wherein a plurality of pads are disposed in the connection region; and a second semiconductor chip disposed on the first semiconductor chip, wherein the plurality of pads include: a first bonding pad for connection with an external circuit; and a first probing pad adjacent to the first bonding pad and for an electrical die sorting (EDS) test, and wherein the second semiconductor chip includes: a first space overlapping the first bonding pad in a vertical direction and in which at least a portion of an electrostatic discharge protection circuit is formed.
1 . An image sensor comprising:
a first chip comprising a pixel array region and a connection region around the pixel array region;
a second chip disposed on the first chip and comprising an input and output circuit;
a first bonding pad for connection with an external circuit; and
a first probing pad adjacent to the first bonding pad and for an electrical die sorting (EDS) test,
wherein the second chip comprises:
a first space overlapping the first bonding pad in a vertical direction;
a second space overlapping the first probing pad in the vertical direction; and
a third space adjacent to at least one of the first space or the second space in a horizontal direction, and in which at least a portion of the input and output circuit is formed, and
wherein the first bonding pad and the first probing pad are disposed on the connection region in a plan view.
2 . The image sensor of claim 1 , wherein the first chip is connected to the second chip through metal electrodes.
3 . The image sensor of claim 2 , further comprising:
a plurality of power lines disposed to pass through the third space in the plan view and being connected to the input and output circuit.
4 . The image sensor of claim 1 , wherein the first chip is connected to the second chip through a through-silicon-via.
5 . The image sensor of claim 4 , further comprising:
a second bonding pad for connection with the external circuit; and
a second probing pad adjacent to the second bonding pad and for the EDS test.
6 . The image sensor of claim 5 , wherein the first bonding pad and the first probing pad form a first pad-pair, and
wherein the second bonding pad and the second probing pad form a second pad-pair having a similar shape to the first pad-pair.
7 . The image sensor of claim 6 , wherein the metal electrodes are disposed on the connection region in the plan view.
8 . The image sensor of claim 1 , further comprising:
an electrostatic discharge protection circuit, and
wherein at least a portion of the electrostatic discharge protection circuit is formed in the first space.
9 . The image sensor of claim 1 , wherein the first chip further comprises:
a dummy wiring layer disposed over the first bonding pad.
10 . The image sensor of claim 9 , further comprising:
a connection bump disposed on the first bonding pad connected to the external circuit.
11 . An image sensor comprising:
a first chip comprising a pixel array region, a first connection region disposed on a first side of the pixel array region in a plan view, and a second connection region disposed on a second side of the pixel array region in the plan view;
a second chip disposed on the first chip and comprising an input and output circuit;
a first bonding pad for connection with an external circuit;
a second bonding pad for connection with the external circuit;
a first probing pad for an electrical die sorting (EDS) test; and
a second probing pad for the EDS test,
wherein the first bonding pad and the first probing pad are disposed on the first connection region in the plan view,
wherein the second bonding pad and the second probing pad are disposed on the second connection region in the plan view, and
wherein the pixel array region is disposed between the first connection region and the second connection region.
12 . The image sensor of claim 11 , wherein the first chip is connected to the second chip through metal electrodes.
13 . The image sensor of claim 11 , wherein the first chip is connected to the second chip through a through-silicon-via.
14 . The image sensor of claim 11 , wherein at least a portion of the input and output circuit is not vertically overlapping with the first bonding pad in the plan view.
15 . The image sensor of claim 11 , wherein at least a portion of the input and output circuit is not vertically overlapping with the second bonding pad in the plan view.
16 . The image sensor of claim 11 , wherein the second chip further comprises:
a first space overlapping the first bonding pad in a vertical direction;
a second space overlapping the first probing pad in the vertical direction; and
a third space adjacent to at least one of the first space or the second space in a horizontal direction, and in which at least a portion of the input and output circuit is formed.
17 . The image sensor of claim 16 , further comprising:
a plurality of power lines disposed to pass through the third space in the plan view and being connected to the input and output circuit.
18 . The image sensor of claim 11 , wherein the first probing pad is disposed adjacent to the first bonding pad,
wherein the first probing pad and the first bonding pad form a first pad-pair,
wherein the second probing pad is disposed adjacent to the second bonding pad, and
wherein the second probing pad and the second bonding pad form a second pad-pair having a similar shape to the first pad-pair.
19 . An image sensor comprising:
a first chip comprising a pixel array region, a first connection region disposed on a first side of the pixel array region in a plan view, and a second connection region disposed on a second side of the pixel array region in the plan view;
a second chip disposed on the first chip and comprising an input and output circuit;
a first bonding pad for connection with an external circuit;
a first probing pad adjacent to the first bonding pad and for an electrical die sorting (EDS) test;
a second bonding pad for connection with the external circuit; and
a second probing pad adjacent to the second bonding pad and for the EDS test,
wherein the first bonding pad and the first probing pad are disposed on the first connection region in the plan view,
wherein the second bonding pad and the second probing pad are disposed on the second connection region in the plan view,
wherein the pixel array region is disposed between the first connection region and the second connection region,
wherein the first probing pad and the first bonding pad form a first pad-pair, and
wherein the second probing pad and the second bonding pad form a second pad-pair having a similar shape to the first pad-pair.
20 . The image sensor of claim 19 , wherein the first chip is connected to the second chip through metal electrodes.