3D semiconductor device and structure
A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; and a via disposed through the second level, where the via has a diameter of less than 450 nm, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the third metal layer by at least 50%.
1. A semiconductor device, the device comprising:
a first silicon layer comprising a first single crystal silicon layer;
a first metal layer disposed over said first single crystal silicon layer;
a second metal layer disposed over said first metal layer;
a third metal layer disposed over said second metal layer;
a second level comprising a plurality of transistors, said second level disposed over said third metal layer;
a fourth metal layer disposed over said second level;
a fifth metal layer disposed over said fourth metal layer; and
a via disposed through said second level,
wherein said via has a diameter of less than 450 nm, and
wherein a typical thickness of said fifth metal layer is greater than a typical thickness of said third metal layer by at least 50%.
2. The device according to claim 1 ,
wherein a typical thickness of said second level is less than two microns.
3. The device according to claim 1 ,
wherein said fourth metal layer is aligned to said first metal layer with a less than 40 nm alignment error.
4. The device according to claim 1 ,
wherein at least one of said plurality of transistors comprises a metal gate.
5. The device according to claim 1 ,
wherein a typical thickness of said second metal layer is greater than a typical thickness of said third metal layer by at least 50%.
6. The device according to claim 1 ,
wherein a typical thickness of said fifth metal layer is greater than a typical thickness of said fourth metal layer by at least 50%.
7. The device according to claim 1 ,
wherein said fifth metal layer comprises a portion of a global power distribution grid.
8. A semiconductor device, the device comprising:
a first silicon layer comprising a first single crystal silicon layer;
a first metal layer disposed over said first single crystal silicon layer;
a second metal layer disposed over said first metal layer;
a third metal layer disposed over said second metal layer;
a second level comprising a plurality of transistors, said second level disposed over said third metal layer;
a fourth metal layer disposed over said second level;
a fifth metal layer disposed over said fourth metal layer; and
a via disposed through said second level,
wherein said via has a diameter of less than 450 nm, and
wherein a typical thickness of said fifth metal layer is greater than a typical thickness of said fourth metal layer by at least 50%.
9. The device according to claim 8 ,
wherein a typical thickness of said second level is less than two microns.
10. The device according to claim 8 ,
wherein said fourth metal layer is aligned to said first metal layer with a less than 40 nm alignment error.
11. The device according to claim 8 ,
wherein at least one of said plurality of transistors comprises a metal gate.
12. The device according to claim 8 ,
wherein a typical thickness of said second metal layer is greater than a typical thickness of said third metal layer by at least 50%.
13. The device according to claim 8 ,
wherein a typical thickness of said fifth metal layer is greater than a typical thickness of said third metal layer by at least 50%.
14. The device according to claim 8 ,
wherein said fifth metal layer comprises a portion of a global power distribution grid.
15. A semiconductor device, the device comprising:
a first silicon layer comprising a first single crystal silicon layer;
a first metal layer disposed over said first single crystal silicon layer;
a second metal layer disposed over said first metal layer;
a third metal layer disposed over said second metal layer;
a second level comprising a plurality of transistors, said second level disposed over said third metal layer;
a fourth metal layer disposed over said second level;
a fifth metal layer disposed over said fourth metal layer; and
a via disposed through said second level,
wherein said second level thickness is less than two microns, and
wherein a typical thickness of said fifth metal layer is greater than a typical thickness of said third metal layer by at least 50%.
16. The device according to claim 15 ,
wherein said via has a diameter of less than 450 nm.
17. The device according to claim 15 ,
wherein said fourth metal layer is aligned to said first metal layer with a less than 40 nm alignment error.
18. The device according to claim 15 ,
wherein said second level comprises a single silicon crystal layer.
19. The device according to claim 15 ,
wherein a typical thickness of said second metal layer is greater than a typical thickness of said third metal layer by at least 50%.
20. The device according to claim 15 ,
wherein a typical thickness of said fifth metal layer is greater than a typical thickness of said fourth metal layer by at least 50%.