Semiconductor memory device, memory system, and write method

1. A memory system comprising:

a semiconductor memory device having a first memory region including a first memory cell capable of holding at least 4-bit data and a second memory region including a plurality of second memory cells capable of holding at least 1-bit data;

a controller configured to control a first write operation and a second write operation based on the 4-bit data in the semiconductor memory device; and

at least one wiring connecting the semiconductor memory device and the controller,

wherein:

the controller includes a conversion circuit which converts the 4-bit data into n-bit data, with n being an integer,

the semiconductor memory device includes a recovery controller configured to recover the 4-bit data based on the converted n-bit data and data written in the first memory cell by the first write operation,

when the controller detects power shutdown, the conversion circuit converts the 4-bit data used for the first write operation into the n-bit data, and

the controller instructs the semiconductor memory device to write each of the n-bit data in different second memory cells of the plurality of second memory cells.

2. A semiconductor memory device comprising:

a memory cell array including a first memory cell capable of holding at least n-bit data, with n being an integer that is at least 4;

a conversion circuit configured to recover the n-bit data based on m-bit data generated by converting the n-bit data and data written in the first memory cell, with m being an integer that is smaller than n; and

at least one pad connectable with an outside of the semiconductor memory device,

wherein:

an operation of writing the n-bit data in the first memory cell includes a first write operation and a second write operation,

the first write operation is executed based on the n-bit data that is received from the outside, and

the second write operation is executed based on the n-bit data that is recovered by the conversion circuit.

3. The memory system according to claim 1 , wherein when the controller detects power shutdown before the 4-bit data is written into the first memory cell, the controller instructs the semiconductor memory device to perform write of 1-bit data in each of four second memory cells of the plurality of second memory cells using the 4-bit data.

4. The memory system according to claim 1 , wherein when the controller detects power shutdown after 2-bit data of the 4-bit data is written into the first memory cell, the controller instructs the semiconductor memory device to perform write of 1-bit data in each of two second memory cells of the plurality of second memory cells using remaining 2-bit data of the 4-bit data.

5. The memory system according to claim 1 , wherein:

the semiconductor memory device further includes a memory cell array including a plurality of memory cells including the first memory cell and the second memory cells, and

the semiconductor memory device further includes at least one of (i) a plurality of word lines respectively connected to gates of the memory cells, or (ii) a plurality of select gate lines respectively connected to one of ends of the memory cells.

6. The memory system according to claim 5 , wherein each of the plurality of memory cells includes:

a semiconductor layer;

a first insulating layer contacting the semiconductor layer;

a charge trap layer contacting the first insulating layer; and

a second insulating layer contacting the charge trap layer.

7. The memory system according to claim 6 , wherein after power recovery, the controller instructs the semiconductor memory device to perform a read operation of the n-bit data written in the second memory region, a recovery operation of the 4-bit data, and the second write operation.

8. The memory system according to claim 6 , wherein:

a threshold voltage of the first memory cell is included in one of a plurality of threshold distributions corresponding to the 4-bit data, and

assignment of the n-bit data to the plurality of threshold distributions differs by 1 bit between the threshold distributions that are adjacent to each other.

9. The memory system according to claim 1 , wherein when the controller does not detect power shutdown after the first write operation, the controller instructs the semiconductor memory device to perform the second write operation to write the 4-bit data in the first memory cell.

10. The semiconductor memory device according to claim 2 , wherein:

the semiconductor memory device further includes a memory cell array including a plurality of memory cells including the first memory cell and the second memory cells, and

the semiconductor memory device further includes at least one of (i) a plurality of word lines respectively connected to gates of the memory cells, or (ii) a plurality of select gate lines respectively connected to one of ends of the memory cells.

11. The semiconductor memory device according to claim 10 , wherein each of the plurality of memory cells includes:

a semiconductor layer;

a first insulating layer contacting the semiconductor layer;

a charge trap layer contacting the first insulating layer; and

a second insulating layer contacting the charge trap layer.

12. The semiconductor memory device according to claim 11 , wherein:

after the first write operation, the conversion circuit converts the 4-bit data into the n-bit data, and the converted n-bit data is outputted to the outside, and

before the second write operation, the conversion circuit recovers the 4-bit data based on the n-bit data that is received from the outside and the data read from the first memory cell.

13. The semiconductor memory device according to claim 2 , wherein:

the memory cell array further includes a plurality of second memory cells capable of holding at least 1-bit data,

each item of the n-bit data is written in a different second memory cell of the plurality of second memory cells, and

before the second write operation, the conversion circuit recovers the n-bit data based on the n-bit data read from the second memory cells and the data read from the first memory cell.

14. The semiconductor memory device according to claim 2 , wherein the conversion circuit recovers the n-bit data based on the generated m-bit data and (n-m)-bit data received from the outside.

15. The semiconductor memory device according to claim 14 , wherein n is 4, and m is 2.

16. A method for controlling a semiconductor memory device, the semiconductor memory device including (i) a memory cell array including a first memory cell capable of holding at least n-bit data, with n being an integer that is at least 4, (ii) a conversion circuit configured to recover the n-bit data based on m-bit data generated by converting the n-bit data and data written in the first memory cell, with m being an integer that is smaller than n, and (iii) at least one pad connectable with an outside of the semiconductor memory device, and the method comprising:

receiving the n-bit data from the outside;

performing a first write operation to the first memory cell based on the n-bit data that is received from the outside;

recovering the n-bit data using the conversion circuit; and

performing a second write operation to the first memory cell based on the n-bit data that is recovered by the conversion circuit, thereby writing the n-bit data in the first memory cell.