3D semiconductor device and structure with oxide bonding
A semiconductor device, the device including: a first silicon layer including first single crystal silicon; an isolation layer disposed over the first silicon layer; a first metal layer disposed over the isolation layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the isolation layer includes an oxide to oxide bond surface, where the plurality of transistors include a second single crystal silicon region; and a third metal layer disposed over the first level, where a typical first thickness of the third metal layer is at least 50% greater than a typical second thickness of the second metal layer.
1. A semiconductor device, the device comprising:
a first silicon layer comprising first single crystal silicon;
an isolation layer disposed over said first silicon layer;
a first metal layer disposed over said isolation layer;
a second metal layer disposed over said first metal layer;
a first level comprising a plurality of transistors, said first level disposed over said second metal layer,
wherein said isolation layer comprises an oxide to oxide bond surface,
wherein said plurality of transistors comprise a second single crystal silicon region; and
a third metal layer disposed over said first level,
wherein a typical first thickness of said third metal layer is at least 50% greater than a typical second thickness of said second metal layer.
2. The device according to claim 1 , further comprising:
a plurality of capacitors,
wherein said plurality of capacitors comprise functioning as a decoupling capacitor to mitigate power supply noise.
3. The device according to claim 1 , further comprising:
a plurality of vias disposed through said first level,
wherein at least one of said plurality of vias comprises a diameter of less than 450 nm.
4. The device according to claim 1 , further comprising:
a plurality of vias disposed through said first level,
wherein at least one of said plurality of vias comprises a contact to at least one of said plurality of transistors.
5. The device according to claim 1 ,
wherein a typical thickness of said first level is less than two microns.
6. The device according to claim 1 ,
wherein at least one of said plurality of transistors comprises at least a two sided gate.
7. The device according to claim 1 , further comprising:
a third metal layer disposed over said first level; and
a fourth metal layer disposed over said third metal layer,
wherein said fourth metal layer is aligned to said first metal layer with a less than 40 nm alignment error.
8. A semiconductor device, the device comprising:
a first level comprising a plurality of transistors,
wherein said plurality of transistors comprise first single crystal silicon;
a first metal layer disposed over said first level;
a second metal layer disposed over said first metal layer;
an isolation layer disposed over said second metal layer;
a first silicon layer comprising second single crystal silicon,
wherein said first silicon layer is disposed over said isolation layer, and
wherein said isolation layer comprises an oxide to oxide bonding surface;
a plurality of capacitors; and
a third metal layer disposed under said first level,
wherein a typical first thickness of said third metal layer is at least 50% greater than a typical second thickness of said first metal layer.
9. The device according to claim 8 ,
wherein said plurality of capacitors comprise functioning as a decoupling capacitor to mitigate power supply noise.
10. The device according to claim 8 , further comprising:
a plurality of vias disposed through said first level,
wherein at least one of said plurality of vias comprise a diameter of less than 450 nm.
11. The device according to claim 8 , further comprising:
a plurality of vias disposed through said first level,
wherein at least one of said plurality of vias comprise contact to at least one of said plurality of transistors.
12. The device according to claim 8 ,
wherein a typical thickness of said first level is less than two microns.
13. The device according to claim 8 ,
wherein at least one of said plurality of transistors comprises at least a two sided gate.
14. The device according to claim 8 , further comprising:
a third metal layer disposed under said first level; and
a fourth metal layer disposed under said third metal layer,
wherein said fourth metal layer is aligned to said first metal layer with a less than 40 nm alignment error.
15. A semiconductor device, the device comprising:
a first level comprising a plurality of transistors,
wherein said plurality of transistors comprise first single crystal silicon;
a first metal layer disposed over said first level;
a second metal layer disposed over said first metal layer;
an isolation layer disposed over said second metal layer;
a first silicon layer comprising second single crystal silicon disposed over said isolation layer,
wherein said isolation layer comprises an oxide to oxide bonding surface;
a plurality of vias disposed through said first level; and
a third metal layer disposed under said first level,
wherein a typical first thickness of said third metal layer is at least 50% greater than a typical second thickness of said first metal layer.
16. The device according to claim 15 ,
wherein at least one of said vias comprise contact to at least one of said plurality of transistors.
17. The device according to claim 15 , further comprising:
a plurality of vias disposed through said first level,
wherein at least one of said plurality of vias comprises a diameter of less than 450 nm.
18. The device according to claim 15 , further comprising:
a plurality of capacitors,
wherein said plurality of capacitors comprise functioning as a decoupling capacitor to mitigate power supply noise.
19. The device according to claim 15 ,
wherein a typical thickness of said first level is less than two microns.
20. The device according to claim 15 ,
wherein at least one of said plurality of transistors comprises at least a two sided gate.