Semiconductor devices
A semiconductor device is provided. The semiconductor device includes: a substrate including an active region; a gate structure intersecting the active region on the substrate; channel layers on the active region, spaced apart from each other and surrounded by the gate structure; and a source/drain region on the active region adjacent the gate structure and connected to the plurality of channel layers. The source/drain region includes: a first semiconductor layer on side surfaces of the channel layers; a diffusion barrier layer on an upper region of the first semiconductor layer and including carbon, wherein an upper surface of a first channel layer that is a lowermost channel layer among the plurality of channel layers is provided between the substrate and a lower end of the diffusion barrier layer; and a second semiconductor layer on the diffusion barrier layer and the first semiconductor layer.
1. A semiconductor device comprising:
a substrate comprising an active region extending in a first direction;
a gate structure extending in a second direction and intersecting the active region, on the substrate;
a plurality of channel layers on the active region, spaced apart from each other in a third direction perpendicular to an upper surface of the substrate, and surrounded by the gate structure; and
a source/drain region on the active region adjacent the gate structure and connected to the plurality of channel layers,
wherein the source/drain region comprises:
a first semiconductor layer on side surfaces of the plurality of channel layers;
a diffusion barrier layer on an upper region of the first semiconductor layer and comprising carbon, wherein an upper surface of a first channel layer that is a lowermost channel layer among the plurality of channel layers is provided between the substrate and a lower end of the diffusion barrier layer; and
a second semiconductor layer on the diffusion barrier layer and the first semiconductor layer.
2. The semiconductor device of claim 1 , wherein the lower end of the diffusion barrier layer is between an upper surface and a lower surface of a second channel layer disposed second from a top among the plurality of channel layers.
3. The semiconductor device of claim 1 , wherein the diffusion barrier layer extends in a direction oblique to the first direction and the third direction.
4. The semiconductor device of claim 1 , wherein the diffusion barrier layer extends along a crystal plane in the upper region of the first semiconductor layer.
5. The semiconductor device of claim 4 , wherein the crystal plane is a {111} plane.
6. The semiconductor device of claim 1 , wherein a thickness of the diffusion barrier layer is in a range of about 0.1 nm to about 5.0 nm.
7. The semiconductor device of claim 1 , wherein a carbon (C) concentration of the diffusion barrier layer is in a range of about 1×10 18 /cm 3 to about 5×10 21 /cm 3 .
8. The semiconductor device of claim 1 , wherein the first semiconductor layer has a first thickness in the upper region and a second thickness greater than the first thickness in a lower region between the substrate and the upper region.
9. The semiconductor device of claim 1 , wherein the first semiconductor layer has a third thickness on the side surfaces of the plurality of channel layers, and has a fourth thickness greater than the third thickness on an upper surface of the active region.
10. The semiconductor device of claim 1 , wherein the first semiconductor layer has a side surface convexly protruding toward the gate structure, below each of the plurality of channel layers.
11. The semiconductor device of claim 1 , wherein a concentration of impurities in the second semiconductor layer is higher than a concentration of impurities in the first semiconductor layer.
12. The semiconductor device of claim 1 , wherein a germanium (Ge) concentration of the second semiconductor layer is higher than a germanium (Ge) concentration of the first semiconductor layer.
13. The semiconductor device of claim 1 , further comprising a contact plug that extends into an upper portion of the source/drain region,
wherein in the first direction, the lower end of the diffusion barrier layer is spaced apart from the contact plug by a first distance, and an upper end of the diffusion barrier layer is spaced apart from the contact plug by a second distance greater than the first distance.
14. The semiconductor device of claim 1 , wherein the source/drain region further comprises a third semiconductor layer between the first semiconductor layer and the second semiconductor layer,
wherein the third semiconductor layer is provided on the diffusion barrier layer.
15. A semiconductor device comprising:
a substrate comprising an active region extending in a first direction;
a gate structure on the substrate, intersecting the active region and extending in a second direction; and
a source/drain region provided in a recess region defined by the active region adjacent the gate structure,
wherein the source/drain region comprises:
a first semiconductor layer on an inner side surface of the recess region;
diffusion barrier layers on upper ends of the first semiconductor layer and extending in directions oblique to the first direction; and
a second semiconductor layer on the diffusion barrier layers and the first semiconductor layer, and
wherein the diffusion barrier layers are spaced apart from each other in the source/drain region in the first direction.
16. The semiconductor device of claim 15 , wherein the first semiconductor layer has a first thickness in a region in contact with the diffusion barrier layers, and a second thickness greater than the first thickness in a region between the substrate and the diffusion barrier layers.
17. The semiconductor device of claim 15 , wherein the diffusion barrier layers comprise carbon (C), and at least one of silicon (Si) or germanium (Ge).
18. The semiconductor device of claim 15 , further comprising a contact plug that extends into an upper portion of the source/drain region,
wherein the diffusion barrier layers are spaced apart from the contact plug.
19. A semiconductor device comprising:
a substrate comprising an active region extending in a first direction;
a gate structure on the substrate, intersecting the active region, and extending in a second direction;
a plurality of channel layers on the active region, spaced apart from each other in a third direction perpendicular to an upper surface of the substrate, and surrounded by the gate structure; and
a source/drain region on the active region adjacent the gate structure, and connected to the plurality of channel layers,
wherein the source/drain region comprises:
a first semiconductor layer on side surfaces of the plurality of channel layers;
a second semiconductor layer on the first semiconductor layer; and
a plurality of diffusion barrier layers between the first semiconductor layer and the second semiconductor layer.
20. The semiconductor device of claim 19 , wherein a first channel layer, among the plurality of channel layers, is provided between the substrate and lower ends of the plurality of diffusion barrier layers.