Nanosheet channel-to-source and drain isolation
A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
1. A method of fabricating a nanosheet semiconductor device, the method comprising:
providing a nanosheet stack on a substrate;
etching the nanosheet stack to form nanosheet fins extending in a first direction;
cutting at least one of the nanosheet fins to form an opening between a first nanosheet fin and an adjacent second nanosheet fin, wherein the first and second nanosheet fins are in-line;
depositing dielectric material in the opening to form a first dielectric region between the first and second nanosheet fins;
forming a dummy gate stack extending in a second direction perpendicular to the first direction over a portion of the first nanosheet fin;
etching the first nanosheet fin using the dummy gate stack as an etch-mask to remove a portion of the first nanosheet fin between:
the dummy gate stack; and
the first dielectric region; and
epitaxially forming a source-drain region, wherein:
a first side of the source-drain region contacts nanosheets of the first nanosheet fin; and
a second opposite side of the source-drain region contacts the first dielectric region.
2. The method of claim 1 , wherein the nanosheet stack comprises alternating Si and SiGe layers, and the source-drain region contacts nanosheets comprising Si layers.
3. The method of claim 2 , further comprising:
before depositing dielectric material in the opening between the first and second nanosheet fins, recessing the SiGe layers to form first divots in the first and second nanosheet fins.
4. The method of claim 2 , further comprising:
subsequent to etching the first nanosheet fin using the dummy gate stack as an etch-mask and prior to epitaxially forming the source-drain region, recessing the SiGe layers of the first nanosheet fin to form second divots in the first nanosheet fin.
5. The method of claim 4 , further comprising:
subsequent to forming the second divots in the first nanosheet fin, forming dielectric inner spacers in the second divots.
6. The method of claim 5 , wherein the dielectric inner spacers comprise Si and N.
7. The method of claim 5 , wherein the dielectric inner spacers comprise Si and O.
8. The method of claim 5 , wherein the dielectric inner spacers comprise Si and C.
9. The method of claim 5 , wherein the dielectric inner spacers comprise Si and B.
10. The method of claim 5 , wherein the dielectric inner spacers comprise Si, O, and N.
11. The method of claim 5 , wherein the dielectric inner spacers comprise Si, B, C, and N.
12. The method of claim 5 , wherein the dielectric inner spacers comprise Si, O, C and N.
13. The method of claim 3 , wherein the first dielectric region comprises first dielectric protrusions corresponding to first divots.
14. The method of claim 13 , further comprising:
subsequent to etching the first nanosheet fin using the dummy gate stack as an etch-mask and prior to epitaxially forming the source-drain region, recessing the SiGe layers of the first nanosheet fin to form second divots in the first nanosheet fin.
15. The method of claim 14 , further comprising:
subsequent to recessing the SiGe layers of the first nanosheet fin to form second divots in the first nanosheet fin, forming dielectric inner spacers in the second divots and second dielectric regions between the first dielectric protrusions of the first dielectric region.
16. The method of claim 15 , wherein materials comprising the dielectric inner spacers and the second dielectric regions are the same.
17. The method of claim 15 , wherein the dielectric inner spacers comprise Si and N.
18. The method of claim 15 , wherein the dielectric inner spacers comprise Si and O.
19. The method of claim 15 , wherein the dielectric inner spacers comprise Si and C.
20. The method of claim 15 , wherein the dielectric inner spacers comprise Si and B.
21. The method of claim 15 , wherein the dielectric inner spacers comprise Si, O, and N.
22. The method of claim 15 , wherein the dielectric inner spacers comprise Si, B, C, and N.
23. The method of claim 15 , wherein the dielectric inner spacers comprise Si, O, C and N.