Switching time reduction of an RF switch
A switching component and switch assembly. The switching component comprises a first control node, a common node, a plurality of intermediate nodes, a second control node, and a capacitive node; a plurality of transistors connected in series between the control node and the common node, one of the plurality of intermediate nodes being defined between each series connected pair of transistors, each transistor of the plurality of transistors having a gate coupled to the second control node; and a plurality of capacitive components, one capacitive component being coupled between each intermediate node and the capacitive node, a voltage at the capacitive node being configured to be varied with a voltage at the second control node such that, at each intermediate node, the capacitive component is configured to accrue an opposite charge to the transistors.
1. A switching component for use in a switch assembly, the switching component comprising:
a first control node, a common node, a plurality of intermediate nodes, a second control node, and a capacitive node;
a plurality of transistors connected in series between the first control node and the common node, each respective intermediate node of the plurality of intermediate nodes being defined between each respective series connected pair of transistors of the plurality of transistors, each transistor of the plurality of transistors having a gate coupled to the second control node;
a first common resistor between the first control node and the common node and in parallel with the plurality of transistors; and
a plurality of capacitive components, each respective capacitive component of the plurality of capacitive components being coupled between a respective intermediate node of the plurality of intermediate nodes and the capacitive node, a voltage at the capacitive node being configured to be varied with a voltage at the second control node such that, at each respective intermediate node, a respective capacitive component is configured to accrue an opposite charge to a corresponding series connected pair of transistors of the plurality of transistors.
2. The switching component of claim 1 wherein each capacitive component of the plurality of capacitive components is configured to release its accrued charge when the series connected pair of transistors connected to a corresponding intermediate node are transitioned from an OFF state to an ON state.
3. The switching component of claim 1 wherein each intermediate node of the plurality of intermediate nodes is connected to a respective first transistor having a first parasitic capacitance between the gate of the respective first transistor and a respective intermediate node and a respective second transistor having a second parasitic capacitance between the gate of the respective second transistor and the respective intermediate node; and
wherein each capacitive component has a capacitance between the respective intermediate node and the capacitive node, wherein for each respective intermediate node the capacitance of the connected capacitive component is equal or approximately equal to the sum of the first and second parasitic capacitances.
4. The switching component of claim 3 wherein, for each intermediate node of the plurality of intermediate nodes, the respective first transistor has a drain connected to the respective intermediate node and the respective second transistor has a source connected to the respective intermediate node, and wherein the first parasitic capacitance is formed between the gate of the respective first transistor and the drain of the respective first transistor and wherein the second parasitic capacitance is formed between the gate of the respective second transistor and the source of the respective second transistor.
5. The switching component of claim 1 wherein the first common resistor includes a plurality of resistive elements, and wherein each transistor of the plurality of transistors has a corresponding resistive element of the plurality of resistive elements connected in parallel with it such that each transistor is configured to selectively bypass its corresponding resistive element.
6. The switching component of claim 1 wherein the plurality of capacitive components are capacitors; or wherein the plurality of capacitive components are transistors, wherein for each of the transistors of the plurality of capacitive components the source and drain are connected.
7. A switch assembly for a radio frequency signal, the switch assembly comprising:
a first node coupled to an input of the switch assembly, a second node coupled to an output of the switch assembly, a first control node, a second control node, a common node, a plurality of intermediate nodes, and a capacitive node;
a first switch having a first plurality of transistors coupled between the first and second nodes, each transistor of the first plurality of transistors having a gate, a drain, and a source, each gate of the first plurality of transistors being coupled to the common node;
a second switch coupled between the first control node and the common node, the second switch having a second plurality of transistors connected in series between the first control node and the common node, one of the plurality of intermediate nodes being defined between each series connected pair of transistors of the second plurality of transistors, each transistor of the second plurality of transistors having a gate coupled to the second control node; and
a plurality of capacitive components, each respective capacitive component of the plurality of capacitive components being coupled between a respective intermediate node of the plurality of intermediate nodes and the capacitive node, a voltage at the capacitive node being configured to be varied with a voltage at the second control node such that, at each respective intermediate node, a respective capacitive component is configured to accrue an opposite charge to a corresponding series connected pair of transistors of the second plurality of transistors.
8. The switch assembly of claim 7 wherein each capacitive component in the second switch is configured to release its accrued charge when the series connected pair of transistors connected to a corresponding intermediate node are transitioned from an OFF state to an ON state.
9. The switch assembly of claim 7 wherein each intermediate node in the second switch is connected to a respective first transistor in the second plurality of transistors, the respective first transistor having a first parasitic capacitance between the gate of the respective first transistor and a respective intermediate node, and a respective second transistor in the second plurality of transistors, the respective second transistor having a second parasitic capacitance between the gate of the respective second transistor and the respective intermediate node; and
wherein each capacitive component has a capacitance between the respective intermediate node and a respective capacitive node, wherein for each intermediate node the capacitance of the connected capacitive component is equal or approximately equal to the sum of the first and second parasitic capacitances.
10. The switch assembly of claim 9 wherein, for each intermediate node in the second switch, the respective first transistor has a drain connected to the respective intermediate node and the respective second transistor has a source connected to the respective intermediate node, and wherein the first parasitic capacitance is formed between the gate of the respective first transistor and the drain of the respective first transistor and wherein the second parasitic capacitance is formed between the gate of the respective second transistor and the source of the respective second transistor.
11. The switch assembly of claim 7 further comprising a first common resistor between the first control node and the common node and in parallel with the second plurality of transistors.
12. The switch assembly of claim 11 wherein the first common resistor includes a plurality of resistive elements, and wherein each transistor of the second plurality of transistors has a corresponding resistive element of the plurality of resistive elements connected in parallel with it such that each transistor in the second plurality of transistors is configured to selectively bypass its corresponding resistive element.
13. The switch assembly of claim 11 wherein the first control node is configured to receive a first control signal that is applied to the gates of transistors of the first plurality of transistors via the second switch through the second plurality of transistors and/or through the plurality of resistors.
14. The switch assembly of claim 13 wherein the first control signal is configured to operate the switch in an ON state by turning on each of the transistors of the first plurality of transistors such that a radio frequency signal received at the first node is provided to the second node.
15. The switch assembly of claim 13 wherein the first control signal is configured to operate the switch in an OFF state by turning off each transistor of the first plurality of transistors such that a radio frequency signal received at the first node is not provided to the second node.
16. The switch assembly of claim 7 wherein the plurality of capacitive components are capacitors; or wherein the plurality of capacitive components are transistors, wherein for each of the transistors of the plurality of capacitive components the source and drain are connected.
17. The switch assembly of claim 7 wherein the second control node is configured to receive a second control signal that is configured to operate the second switch in an OFF state such that the first control signal is applied to the gates of the first plurality of transistors through the plurality of resistors.
18. The switch assembly of claim 7 wherein the second control node is configured to receive a second control signal that is configured to operate the second switch in an ON state such that the common resistor is shorted and such that the first control signal is applied to the gates of the first plurality of transistors through the second plurality of transistors.
19. The switch assembly of claim 18 wherein the second control signal is configured to operate the second switch in the ON state whilst the first control signal is configured to transition the first switch between an ON state and an OFF state.
20. A method of designing a switch assembly for a radio frequency signal, the method comprising:
arranging a first switch having a first plurality of transistors coupled between a first node and a second node, each transistor of the first plurality of transistors having a gate, a drain, and a source, each gate of the first plurality of transistors being coupled to a common node, the first node coupled to an input of the switch assembly, and the second node coupled to an output of the switch assembly;
arranging a second switch coupled between the first control node and the common, the second switch having a second plurality of transistors connected in series between the first control node and the common node, one of the plurality of intermediate nodes being defined between each series connected pair of transistors of the second plurality of transistors, each transistor of the second plurality of transistors having a gate coupled to the second control node;
a plurality of capacitive components, each respective capacitive component of the plurality of capacitive components being connected between a respective intermediate node of the plurality of intermediate nodes and the capacitive node, a voltage at the capacitive node being configured to be varied inversely with a voltage at the second control node such that, at each intermediate node, a respective capacitive component is configured to accrue an opposite charge to a corresponding series connected pair of transistors of the second plurality of transistors;
controlling the second switch to be in an ON state such that a first control signal received by the first control node passes through the second plurality of transistors between the first control node and the common node during a period in which the first switch is transitioning between an ON state and an OFF state; and
controlling the second switch to be in an OFF state such that the first control signal does not pass through the second plurality of transistors between the first control node and the common node during a period in which the first switch is not transitioning between an ON state and an OFF state.