Buffer epitaxial region in semiconductor devices and manufacturing method of the same
View Patent ↗A method includes forming a semiconductor fin protruding from a semiconductor substrate. The semiconductor fin has an epitaxial portion and a mesa portion under the epitaxial portion. The epitaxial portion has a plurality of channel layers interleaved with a plurality of sacrificial layers. The semiconductor substrate has a top surface in (110) crystal plane. The method also includes forming a dummy gate structure across the semiconductor fin, removing at least the epitaxial portion of the semiconductor fin in a region adjacent the dummy gate structure to form a recess, epitaxially growing a buffer semiconductor region in the recess, epitaxially growing a source/drain feature on the buffer semiconductor region, and replacing the dummy gate structure with a metal gate structure. The buffer semiconductor region has a top surface in (110) crystal plane.
1 . A method, comprising:
forming a semiconductor fin protruding from a semiconductor substrate, the semiconductor fin having an epitaxial portion and a mesa portion under the epitaxial portion, the epitaxial portion having a plurality of channel layers interleaved with a plurality of sacrificial layers, the semiconductor substrate having a top surface in (110) crystal plane;
forming a dummy gate structure across the semiconductor fin;
removing at least the epitaxial portion of the semiconductor fin in a region adjacent the dummy gate structure, thereby forming a recess;
epitaxially growing a buffer semiconductor region in the recess, the buffer semiconductor region having a top surface in (110) crystal plane and a facet in (111) crystal plane;
epitaxially growing a source/drain feature on the buffer semiconductor region; and
replacing the dummy gate structure with a metal gate structure.
2 . The method of claim 1 , wherein an angle formed between the facet and a normal direction to the top surface of the semiconductor substrate ranges from about 5° to about 35.5°.
3 . The method of claim 1 , wherein the recess exposes a sidewall of the mesa portion under the dummy gate structure, and wherein the buffer semiconductor region fully covers the sidewall of the mesa portion.
4 . The method of claim 1 , wherein viewing in a lengthwise direction of the semiconductor fin, the buffer semiconductor region partially overlaps with a bottommost sacrificial layer.
5 . The method of claim 4 , wherein the buffer semiconductor region partially overlaps with the bottommost sacrificial layer for a thickness from about 1 nm to about 5 nm.
6 . The method of claim 1 , wherein a dopant concentration of the buffer semiconductor region is less than the semiconductor substrate and the source/drain feature.
7 . The method of claim 1 , wherein the buffer semiconductor region is substantially free of dopants.
8 . The method of claim 1 , wherein the buffer semiconductor region is essentially of silicon.
9 . The method of claim 1 , further comprising:
forming inner spacers interposing the source/drain feature and the metal gate structure, wherein the buffer semiconductor region interfaces with a bottommost inner spacer.
10 . The method of claim 1 , wherein the buffer semiconductor region has a thickness from about 10 nm to about 50 nm.
11 . A method, comprising:
forming a semiconductor fin protruding from a substrate, the substrate having a top surface in (110) crystal plane;
forming a cladding layer on sidewalls of the semiconductor fin;
forming first and second dielectric fins on sidewalls of the cladding layer;
forming a dummy gate structure on the semiconductor fin and the first and second dielectric fins;
recessing the semiconductor fin in a region adjacent to the dummy gate structure, thereby forming a recess;
laterally recessing the cladding layer and a portion of the semiconductor fin exposed in the recess, thereby forming cavities;
depositing dielectric spacers in the cavities;
growing a buffer epitaxial layer in the recess and sandwiched by the first and second dielectric fins, the buffer epitaxial layer having a top surface in (110) crystal plane, the buffer epitaxial layer in physical contact with a bottommost dielectric spacer;
growing a source/drain feature on the buffer epitaxial layer, the source/drain feature including a plurality of epitaxial layers of different dopant concentrations;
depositing a dielectric layer over the source/drain feature; and
replacing the dummy gate structure with a metal gate structure.
12 . The method of claim 11 , wherein the semiconductor fin includes channel layers and sacrificial layers alternatingly disposed in a vertical direction, and wherein a top surface of the buffer epitaxial layer is below a bottom surface of a bottommost channel layer.
13 . The method of claim 11 , wherein the buffer epitaxial layer has a thickness from about 10 nm to about 50 nm.
14 . The method of claim 11 , wherein the buffer epitaxial layer includes a facet in (111) crystal plane, and wherein an angle between the facet and a vertical direction ranges from about 5° to about 35.5°.
15 . The method of claim 11 , wherein the buffer epitaxial layer is free of contact with the first and second dielectric fins.
16 . The method of claim 11 , wherein the buffer epitaxial layer is undoped.
17 . The method of claim 11 , wherein the dielectric layer traps an air gap under a topmost epitaxial layer of the source/drain feature.
18 . A method, comprising:
forming a semiconductor fin protruding from a substrate, the substrate having a top surface in (110) crystal plane;
forming a cladding layer on sidewalls of the semiconductor fin;
forming first and second dielectric fins on sidewalls of the cladding layer;
forming a dummy gate structure on the semiconductor fin and the first and second dielectric fins;
recessing the semiconductor fin in a region adjacent to the dummy gate structure, thereby forming a recess;
growing a buffer epitaxial layer in the recess and sandwiched by the first and second dielectric fins, the buffer epitaxial layer having a top surface in (110) crystal plane and a facet in (111) crystal plane;
growing a source/drain feature on the buffer epitaxial layer;
depositing a dielectric layer over the source/drain feature; and
replacing the dummy gate structure with a metal gate structure, the metal gate structure comprising a titanium-containing material.
19 . The method of claim 18 , wherein the source/drain feature includes at least two epitaxial layers of different dopant concentrations, and one of the two epitaxial layers interposes the buffer epitaxial layer and one of the first and second dielectric fins.
20 . The method of claim 18 , wherein the buffer epitaxial layer has a thickness from about 10 nm to about 50 nm, and wherein an angle between the facet and a vertical direction ranges from about 5° to about 35.5°.