IP Library › Granted Patent US 12,628,665
Granted Patent B2
US 12,628,665 · App. 18/176,369 · Granted May 12, 2026

Semiconductor device

Inventors: Taira Tabakoya (Fuchu Tokyo, JP); Toshihiro Tsujimura (Ota Tokyo, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H10W70/461H10W70/417H10W70/466H10W70/481H10W72/07353H10W72/334H10W90/736
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,628,665
App. No.
18/176,369
Granted
May 12, 2026
Kind
B2
Abstract

A semiconductor device can include: a semiconductor chip including a first and second surface, a first electrode on the first surface, an active area on the second surface, a second electrode on the second surface, and a third electrode on the second surface; a first conductive member in the active area of the semiconductor chip and electrically connected to the semiconductor chip; a second conductive member in a second area and isolated from the first conductive member, the second area an area in which, when viewed from above, with respect to a first area of the active area in which the first conductive member is not provided, circles sharing centers of shortest distances between an outer periphery of the first conductive member and an outer periphery of the active area can be drawn largest in the first area; and a lead terminal connected to the first conductive member.

Claims (36)

1 . A semiconductor device comprising:

a semiconductor chip comprising:

a first surface,

a second surface different from the first surface, the second surface comprising an active area comprising a first area and a second area in the first area,

a first electrode provided on the first surface,

a second electrode provided on the second surface, and

a third electrode provided on the second surface;

a first conductor provided in the active area of the semiconductor chip and electrically connected to the semiconductor chip;

a second conductor provided in the second area and isolated from the first conductor, when viewed from above, the second area being an area in which the first conductor is not provided, the second area being a portion of the first area having an area for circles with larger diameters between an outer periphery of the first conductor and an outer periphery of the active area compared to circles drawn in the first area between the outer periphery of the first conductor and the outer periphery of the active area;

a lead terminal connected to the first conductor;

an insulating film provided above the second electrode and having a first opening; and

a first connector provided in the first opening and connecting the first conductor and the semiconductor chip,

wherein the insulating film further has a second opening, and

the second conductor is connected to the second electrode via a second connector in the second opening.

2 . The semiconductor device according to claim 1 , wherein the second conductor is connected to the first connector.

3 . The semiconductor device according to claim 1 , wherein the first connector has a void.

4 . A semiconductor device comprising:

a semiconductor chip comprising:

a first surface,

a second surface different from the first surface, the second surface comprising an active area comprising a first area and a second area in the first area,

a first electrode provided on the first surface,

a second electrode provided on the second surface, and

a third electrode provided on the second surface;

a first conductor provided in the active area of the semiconductor chip and electrically connected to the semiconductor chip;

a second conductor provided in the second area and isolated from the first conductor, when viewed from above, the second area being an area in which the first conductor is not provided, the second area being a portion of the first area having an area for circles with larger diameters between an outer periphery of the first conductor and an outer periphery of the active area compared to circles drawn in the first area between the outer periphery of the first conductor and the outer periphery of the active area;

a lead terminal connected to the first conductor; and

a third conductor provided in the second area in a manner of being isolated from the first conductor and the second conductor, wherein

when viewed from above, the first conductor is provided between the second conductor and the third electrode and between the third conductor and the third electrode, and

the second conductor and the third conductor are provided symmetrically with respect to a third plane passing through the third electrode and perpendicular to the first surface.

5 . The semiconductor device according to claim 4 , wherein

when viewed from above, the active area has a U-shape or a squared U-shape, and

when viewed from above, the third electrode is provided inside the U-shape or the squared U-shape of the active area.

6 . The semiconductor device according to claim 4 , wherein

when viewed from above, the first conductor has a U-shape or a squared U-shape,

the second conductor and the third conductor are provided outside the U-shape or the squared U-shape of the first conductor, and

the third electrode is provided inside the U-shape or the squared U-shape of the first conductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2023
From: TABAKOYA, TAIRA; TSUJIMURA, TOSHIHIRO
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 063795/0441 →
Priority Claims (1)
JP 2022-151661 · Sep 22, 2022 · national
Continuity (1)
Related Publication 20240105562A1 · Mar 28, 2024
References Cited (19)
US 10217689B2 · Yasutake · 2019 [cited by applicant]
US 11367715B2 · Tonedachi · 2022 [cited by applicant]
US 20070290336A1 · Sun · 2007 [cited by examiner]
US 20110241198A1 · Azuma · 2011 [cited by examiner]
US 20150214139A1 · Miyakawa · 2015 [cited by examiner]
US 20170179108A1 · Okuda et al. · 2017 [cited by applicant]
US 20200402946A1 · Takada · 2020 [cited by applicant]
US 20210280532A1 · Suzuki · 2021 [cited by examiner]
US 20210294952A1 · Imi et al. · 2021 [cited by applicant]
JP 2008306115A · 2008 [cited by applicant]
JP 2017010440 · 2017 [cited by applicant]
JP 2017130540 · 2017 [cited by applicant]
JP 2017147433A · 2017 [cited by applicant]
JP 2020205380A · 2020 [cited by applicant]
JP 2021089971 · 2021 [cited by applicant]
JP 2021149855 · 2021 [cited by applicant]
JP 2021152698 · 2021 [cited by applicant]
JP 2022033586 · 2022 [cited by applicant]
Office Action issued in Japanese Patent Application No. 2022-151661 dated Aug. 26, 2025, in 8 pages. [cited by applicant]