Semiconductor devices including a lower semiconductor package, an upper semiconductor package on the lower semiconductor package, and a connection pattern between the lower semiconductor package and the upper semiconductor package

1. A semiconductor device, comprising:

a lower semiconductor package, the lower semiconductor package including a lower base and a first lower chip on the lower base, the first lower chip including a chip pad, a pad structure, a first heat sink pattern, and a redistribution line configured to electrically connect the chip pad and the pad structure to each other;

an upper semiconductor package including at least one chip and on the lower semiconductor package;

a connection pattern between the lower semiconductor package and the upper semiconductor package, the connection pattern configured to electrically connect the lower semiconductor package and the upper semiconductor package to each other;

a second heat sink pattern between the lower semiconductor package and the upper semiconductor package; and

an empty space between the lower semiconductor package and the upper semiconductor package,

wherein at least a portion of a side surface of each of the connection pattern and the second heat sink pattern is exposed by the empty space,

wherein the second heat sink pattern contacts the first heat sink pattern and the upper semiconductor package, and

wherein the second heat sink pattern includes a same material as the connection pattern.

2. The semiconductor device of claim 1 ,

wherein the lower semiconductor package further includes a lower mold layer covering the first lower chip and including a first opening to expose at least a portion of the pad structure and a second opening to expose at least a portion of the first heat sink pattern.

3. The semiconductor device of claim 2 ,

wherein the pad structure includes:

a first pad; and

a second pad on the first pad, and

wherein the chip pad is at a same height level as the first pad.

4. The semiconductor device of claim 3 ,

wherein the first heat sink pattern includes a first pattern and a second pattern on the first pattern,

wherein the first pattern is at a same height level as the first pad,

wherein the first pattern includes a same material as the first pad,

wherein the second pattern is at a same height level as the second pad, and

wherein the second pattern includes a same material as the second pad.

5. The semiconductor device of claim 3 ,

wherein a thickness of the second pad is greater than a thickness of the first pad.

6. The semiconductor device of claim 2 ,

wherein a lower region of the second heat sink pattern contacts the lower mold layer.

7. The semiconductor device of claim 2 ,

wherein the second heat sink pattern is spaced apart from the lower mold layer.

8. The semiconductor device of claim 1 ,

wherein the lower semiconductor package further includes a second lower chip below the first lower chip.

9. The semiconductor device of claim 1 ,

wherein the pad structure includes

a first pad, and

a second pad on the first pad, and

wherein the chip pad, the redistribution line and the first pad are included in a single, continuous instance of material.

10. The semiconductor device of claim 1 ,

wherein the first lower chip further includes

a silicon substrate,

a lower layer on the silicon substrate,

an upper layer on the lower layer, and

an intermediate layer between the lower layer and the upper layer,

wherein the chip pad, the pad structure, and the first heat sink pattern are on the lower layer, and

wherein the upper layer and the intermediate layer have

a first opening that extends through both the upper layer and the intermediate layer to expose at least a portion of the chip pad, and

a second opening that extends through both the upper layer and the intermediate layer to expose at least a portion of a top surface of the pad structure.

11. The semiconductor device of claim 1 ,

wherein the lower base includes a base pad,

wherein the lower semiconductor package further includes a wire configured to electrically connect the chip pad and the base pad to each other, and

wherein the lower semiconductor package further includes a lower mold layer covering the first lower chip and the wire.

12. The semiconductor device of claim 11 ,

wherein the lower semiconductor package further includes:

a second lower chip between the first lower chip and the lower base;

an adhesive layer between the first lower chip and the second lower chip; and

a conductive bump between the second lower chip and the lower base, and

wherein the adhesive layer is in contact with a bottom surface of a silicon substrate of the first lower chip and a top surface of the second lower chip.

13. The semiconductor device of claim 1 ,

wherein the upper semiconductor package further includes:

an upper base below the at least one chip;

an upper pad below the upper base and contacting the connection pattern; and

a dummy pad below the upper base and contacting the second heat sink pattern.

14. A semiconductor device, comprising:

a lower semiconductor package;

an upper semiconductor package including at least one chip and on the lower semiconductor package;

a connection pattern between the lower semiconductor package and the upper semiconductor package, and configured to electrically connect the lower semiconductor package and the upper semiconductor package to each other;

an upper heat sink pattern between the lower semiconductor package and the upper semiconductor package; and

an empty space between the lower semiconductor package and the upper semiconductor package,

wherein at least a portion of a side surface of each of the connection pattern and the upper heat sink pattern is exposed by the empty space,

wherein the lower semiconductor package includes a lower heat sink pattern, a chip pad, a pad structure, a redistribution line configured to electrically connect the chip pad and the pad structure,

wherein at least a portion of the lower heat sink pattern is at a same height level as at least a portion of the pad structure,

wherein the upper heat sink pattern contacts the lower heat sink pattern and the upper semiconductor package, and

wherein the upper heat sink pattern includes a same material as the connection pattern.

15. The semiconductor device of claim 14 ,

wherein the lower semiconductor package further includes a mold layer including a first opening to expose at least an upper portion of the pad structure and a second opening to expose at least an upper portion of the lower heat sink pattern, and

wherein the mold layer vertically overlaps the chip pad and the redistribution line.

16. The semiconductor device of claim 14 ,

wherein the pad structure includes:

a first pad; and

a second pad on the first pad,

wherein the lower heat sink pattern includes:

a first pattern; and

a second pattern on the first pattern,

wherein the first pattern is at a same height level as the first pad,

wherein the first pattern includes a same material as the first pad,

wherein the second pattern is at a same height level as the second pad, and

wherein the second pattern includes a same material as the second pad.

17. The semiconductor device of claim 16 ,

wherein a thickness of the second pad is greater than a thickness of the first pad.

18. The semiconductor device of claim 14 ,

wherein the lower semiconductor package further includes a first lower chip and a second lower chip on the first lower chip, and

wherein the second lower chip includes the lower heat sink pattern, the chip pad, the pad structure, and the redistribution line.

19. The semiconductor device of claim 14 ,

wherein the lower semiconductor package further includes a wire configured to electrically connect the chip pad.

20. The semiconductor device of claim 14 ,

wherein the chip pad does not overlap the pad structure and the connection pattern in a vertical direction perpendicular to an upper surface of the upper semiconductor package.