Method of forming a semiconductor device with air gaps for low capacitance interconnects
A method of forming a semiconductor device with air gaps for low capacitance interconnects. The method includes providing a substrate containing raised metal features with a top area and a sidewall, and a void between the raised metal features, filling the void with a sacrificial fill material, and selectively depositing a blocking layer on the sacrificial fill material. The method further includes depositing a cap layer on the top area of the raised metal features, where the cap layer has an overhang that extends past the sidewall, removing the blocking layer and the sacrificial fill material between the raised metal features, and depositing a dielectric film, where the dielectric film forms an air gap between the raised metal features below the overhang.
1 . A substrate processing method, comprising:
providing a substrate containing raised metal features with a top area and a sidewall, and a void between the raised metal features;
filling the void with a sacrificial fill material;
selectively depositing a blocking layer on the sacrificial fill material;
depositing a cap layer on the top area of the raised metal features, wherein the cap layer has an overhang that extends past the sidewall;
removing the blocking layer and the sacrificial fill material between the raised metal features; and
depositing a dielectric film, wherein the dielectric film forms an air gap between the raised metal features below the overhang.
2 . The method of claim 1 , wherein the cap layer and the dielectric film contain the same dielectric material.
3 . The method of claim 1 , wherein the cap layer and the dielectric film contain different dielectric materials.
4 . The method of claim 1 , wherein the removing includes an anisotropic etching process that removes a portion of the sacrificial fill material and leaves a spacer layer on the sidewall of the raised metal features.
5 . The method of claim 1 , wherein the depositing the dielectric film includes, in any order, conformally depositing a first portion of the dielectric film and non-conformally depositing a second portion of the dielectric film.
6 . The method of claim 1 , wherein the raised metal features include ruthenium metal, molybdenum metal, tungsten metal, copper metal, cobalt metal, a binary metal alloy, or a ternary metal alloys.
7 . The method of claim 1 , wherein the sacrificial fill material includes SiO 2 or SiOC.
8 . The method of claim 1 , wherein the cap layer includes Al 2 O 3 , HfO 2 , SiCN x , TiO 2 , AlON x , AlN x , SiO 2 , SiOC, SiOCN, or a carbon-based layer.
9 . The method of claim 1 , wherein the blocking layer includes a self-assembled monolayer (SAM), a bi-layer SAM, or a carbon-based material.