IP Library › Granted Patent US 12,231,087
Granted Patent B2
US 12,231,087 · App. 18/182,047 · Granted Feb 18, 2025

Body tie optimization for stacked transistor amplifier

Inventors: Simon Edward Willard (Irvine, CA); Chris Olson (Palatine, IL); Tero Tapio Ranta (San Diego, CA)
Assignee: pSemi Corporation
H03F1/0205H01L21/84H01L27/0688H01L27/1203H01L28/40H01L29/0847H01L29/1095H03F1/223H03F1/523H03F3/193H03F3/195H03F3/21H03F2200/108H03F2200/297H03F2200/42H03F2200/451H03F2200/48H03F2200/61H03F2200/75
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Quick Facts
Patent No.
US 12,231,087
App. No.
18/182,047
Granted
Feb 18, 2025
Kind
B2
Abstract

A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

Claims (28)

1. A circuit, comprising:

a transistor stack configured to operate as an amplifier, the transistor stack comprising an input transistor in series connection with at least one transistor, the input transistor configured to receive an input RF signal at a gate of the input transistor;

wherein the input transistor is a body tied transistor having a body that is coupled to a potential, and

wherein the at least one transistor is a floating transistor having a body that is not coupled to a potential.

2. The circuit according to claim 1 , wherein the body of the input transistor is directly connected to a source of the input transistor.

3. The circuit according to claim 1 , wherein the body of the input transistor is coupled to a source of the input transistor through a resistor.

4. The circuit according to claim 1 , wherein the body of the input transistor is coupled to a fixed reference potential through an impedance of a corresponding body tie.

5. The circuit according to claim 1 , wherein the at least one transistor is an output transistor of the amplifier.

6. The circuit according to claim 1 , wherein the at least one transistor is a transistor different from an output transistor of the amplifier.

7. The circuit according to claim 1 , further comprising:

one or more additional transistors in series connection with the input transistor and the at least one transistor.

8. The circuit according to claim 7 , wherein the one or more additional transistors comprise at least one additional body tied transistor having a body that is coupled to a respective potential.

9. The circuit according to claim 7 , wherein each transistor of the one or more additional transistors is a body tied transistor having a respective body that is coupled to a respective potential.

10. The circuit according to claim 9 , wherein the respective body of each transistor of the one or more additional transistors is coupled to the respective potential of a respective source.

11. The circuit according to claim 7 , wherein the one or more additional transistors comprise at least one additional floating transistor having a body that is not coupled to a potential.

12. The circuit according to claim 1 , further comprising:

a gate capacitor connected between a gate of the floating transistor and a reference ground, the gate capacitor configured to allow a gate voltage of the floating transistor to vary along with an RF signal at a drain of the floating transistor.

13. The circuit according to claim 1 , wherein a drain of the floating transistor is coupled to a supply voltage that is configured to vary under control of a control signal.

14. The circuit according to claim 1 , wherein the input transistor and the at least one transistor are metal-oxide-semiconductor (MOS) field effect transistors (FETs), or complementary metal-oxide-semiconductor (CMOS) field effect transistors (FETs).

15. The circuit according to claim 14 , wherein the input transistor and the at least one transistor are fabricated using one of: a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS).

16. The circuit according to claim 14 , wherein the input transistor and the at least one transistor are one of: a) N-type transistors, and b) P-type transistors.

17. An electronic module comprising the circuit of claim 1 .

18. An electronic system comprising the electronic module of claim 17 , wherein the electronic system comprises one of: a) a television, b) a cellular telephone, c) a personal computer, d) a workstation, e) a radio, f) a video player, g) an audio player, h) a vehicle, i) a medical device, and j) other electronic systems.

19. A method for manufacturing a stacked metal-oxide-semiconductor (MOS) power amplifier, the method comprising:

providing a substrate comprising one of: a) silicon-on-insulator substrate, and b) a silicon-on-sapphire substrate; and

manufacturing, on the substrate, a transistor stack configured to operate as the MOS power amplifier, the transistor stack comprising an input transistor in series connection with at least one transistor, the input transistor configured to receive an input RF signal at a gate of the input transistor,

wherein the input transistor is a body tied transistor having a body that is coupled to a potential, and

wherein the at least one transistor is a floating transistor having a body that is not coupled to a potential.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2024
From: WILLARD, SIMON EDWARD; RANTA, TERO TAPIO; OLSON, CHRIS
To: PEREGRINE SEMICONDUCTOR CORPORATION
Reel/Frame 069488/0972 →
CHANGE OF NAME Recorded Dec 4, 2024
From: PEREGRINE SEMICONDUCTOR CORPORATION
To: PSEMI CORPORATION
Reel/Frame 069510/0365 →
Continuity (5)
Continuation 17021878 · Sep 15, 2020
Continuation 16453287 · Jun 26, 2019
Continuation 15839648 · Dec 12, 2017
Continuation 15268257 · Sep 16, 2016
Related Publication 20230283237A1 · Sep 7, 2023
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