Granted Patent B2

US 12,249,390 · App. 18/316,743 · Granted Mar 11, 2025

Inventors: Chieh Lee (Hsinchu, TW); Yi-Ching Liu (Hsinchu, TW); Chia-En Huang (Xinfeng Township, TW); Jen-Yuan Chang (Hsinchu, TW); Yih Wang (Hsinchu, TW)

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.

G11C5/06G11C5/025H01L23/481H10B12/00H10B61/00H10B63/84H10N50/01H10N50/80H10N70/011H10N70/821

Abstract

Claims (32)

1. A memory device, comprising:

a peripheral layer including a plurality of peripheral circuits;

a plurality of memory array layers disposed with respect to the peripheral layer in a vertical direction, each of the plurality of memory array layers corresponding to one of the plurality of peripheral circuits and including a respective memory array, a respective row decoder circuit, and a respective column sensing circuit; and

a plurality of interconnect structures fully extending across the peripheral layer and the memory array layers along the vertical direction, wherein at least a first one of the plurality of interconnect structures operatively couples the peripheral layer to a first one of the memory array layers but is operatively isolated from a second one of the memory array layers.

2. The memory device of claim 1 , wherein a first one of the plurality of peripheral circuits is operatively coupled to the corresponding memory array, the corresponding row decoder circuit, and the corresponding column sensing circuit of the first memory array layer through the at least first interconnect structure.

3. The memory device of claim 1 , wherein a second one of the plurality of peripheral circuits is operatively coupled to the corresponding memory array, the corresponding row decoder circuit, and the corresponding column sensing circuit of the second memory array layer through at least a second one of the plurality of interconnect structures.

4. The memory device of claim 3 , wherein the second interconnect structure is operatively isolated from the first memory array layer.

5. The memory device of claim 1 , wherein each of the memory array layers further includes a space area, and wherein the plurality of interconnect structures pass through the space area.

6. The memory device of claim 1 , wherein the memory array of each of the memory array layers includes a dynamic random access memory (DRAM) array.

7. The memory device of claim 1 , wherein the memory array of each of the memory array layers includes a resistive random access memory (RRAM) array.

8. The memory device of claim 1 , wherein the memory array of each of the memory array layers includes a magnetoresistive random access memory (MRAM) array.

9. The memory device of claim 1 , wherein the plurality of interconnect structures each include a through-silicon-via structure.

10. The memory device of claim 1 , wherein the peripheral layer is disposed immediately below the first memory array layer without any other memory array layer interposed therebetween.

11. A memory device, comprising:

a peripheral layer including a plurality of peripheral circuits;

a plurality of memory array layers disposed with respect to the peripheral layer in a vertical direction, each of the plurality of memory array layers corresponding to one of the plurality of peripheral circuits and including a respective memory array, a respective row decoder circuit, and a respective column sensing circuit; and

a plurality of interconnect structures fully extending across the peripheral layer and the memory array layers along the vertical direction, wherein at least a first one of the plurality of interconnect structures operatively couples the peripheral layer to a first one of the memory array layers but is operatively isolated from a second one of the memory array layers;

wherein the plurality of interconnect structures each include a through-silicon-via structure.

12. The memory device of claim 11 , wherein a first one of the plurality of peripheral circuits is operatively coupled to the corresponding memory array, the corresponding row decoder circuit, and the corresponding column sensing circuit of the first memory array layer through the at least first interconnect structure.

13. The memory device of claim 11 , wherein a second one of the plurality of peripheral circuits is operatively coupled to the corresponding memory array, the corresponding row decoder circuit, and the corresponding column sensing circuit of the second memory array layer through at least a second one of the plurality of interconnect structures.

14. The memory device of claim 13 , wherein the second interconnect structure is operatively isolated from the first memory array layer.

15. The memory device of claim 11 , wherein each of the memory array layers further includes a space area, and wherein the plurality of interconnect structures pass through the space area.

16. The memory device of claim 11 , wherein the memory array of each of the memory array layers includes a dynamic random access memory (DRAM) array.

17. The memory device of claim 11 , wherein the memory array of each of the memory array layers includes a resistive random access memory (RRAM) array.

18. The memory device of claim 11 , wherein the memory array of each of the memory array layers includes a magnetoresistive random access memory (MRAM) array.

19. A memory device, comprising:

a peripheral layer including a plurality of peripheral circuits;

a plurality of memory array layers disposed with respect to the peripheral layer in a vertical direction, each of the plurality of memory array layers corresponding to one of the plurality of peripheral circuits and including a respective memory array, a respective row decoder circuit, and a respective column sensing circuit; and

a plurality of interconnect structures fully extending across the peripheral layer and the memory array layers along the vertical direction, wherein at least a first one of the plurality of interconnect structures operatively couples the peripheral layer to a first one of the memory array layers but is operatively isolated from a second one of the memory array layers;

wherein a first one of the plurality of peripheral circuits is operatively coupled to the corresponding memory array, the corresponding row decoder circuit, and the corresponding column sensing circuit of the first memory array layer through the at least first interconnect structure;

wherein a second one of the plurality of peripheral circuits is operatively coupled to the corresponding memory array, the corresponding row decoder circuit, and the corresponding column sensing circuit of the second memory array layer through at least a second one of the plurality of interconnect structures.

20. The memory device of claim 19 , wherein the second interconnect structure is operatively isolated from the first memory array layer.

Assignments (1)

Continuity (2)

References Cited (13)