Accelerated mathematical engine
Various embodiments of the disclosure relate to an accelerated mathematical engine. In certain embodiments, the accelerated mathematical engine is applied to image processing such that convolution of an image is accelerated by using a two-dimensional matrix processor comprising sub-circuits that include an ALU, output register and shadow register. This architecture supports a clocked, two-dimensional architecture in which image data and weights are multiplied in a synchronized manner to allow a large number of mathematical operations to be performed in parallel.
1 . A matrix processor comprising:
a first input circuit configured to receive input data, wherein the input data is derived from convolving first data and a first plurality of weights, and wherein the input data is organized into individual first vectors;
a second input circuit configured to receive a second plurality of weights, wherein the second plurality of weights are organized into individual second vectors; and
a plurality of sub-circuits configured to convolve the input data and the second plurality of weights for estimating the first data, wherein to convolve the input data and the second plurality of weights, the sub-circuits are configured to accumulate partial dot products associated with the individual first vectors and the individual second vectors, and wherein output associated with the convolution represents a deconvolution.
2 . The matrix processor of claim 1 , wherein each sub-circuit stores a respective output pixel associated with convolving the input data and the second plurality of weights.
3 . The matrix processor of claim 1 , wherein the sub-circuits comprise respective multipliers, adders and accumulators.
4 . The matrix processor of claim 3 , wherein at least a portion of the partial dot products are stored in the accumulators.
5 . The matrix processor of claim 1 , wherein at least a portion of the sub-circuits share a particular encoder, and wherein the particular encoder is a booth encoder.
6 . The matrix processor of claim 1 , wherein the individual first vectors are provided along a first direction of the matrix processor, and wherein the individual second vectors are provided along a second direction of the matrix processor.
7 . The matrix processor of claim 1 , wherein the first input circuit is associated with a first formatter configured to fetch the input data and organize the input data into the individual first vectors.
8 . The matrix processor of claim 1 , wherein the matrix processor implements a state machine configured to identify redundant data.
9 . The matrix processor of claim 1 , wherein the input data comprises image data, LIDAR data, ultrasonic data, or radar data.
10 . The matrix processor of claim 1 , wherein the first plurality of weights and the second plurality of weights are different.
11 . A system comprising:
a first logic circuit configured to format input data into individual first vectors, wherein the input data is derived from convolving a first data and a first plurality of weights;
a second logic circuit configured to format a second plurality of weights into individual second vectors; and
a matrix processor comprising a plurality of sub-circuits configured to convolve the input data and the second plurality of weights for estimating the first data, wherein to convolve the input data and the second plurality of weights, the sub-circuits are configured to accumulate partial dot products associated with the individual first vectors and the individual second vectors.
12 . The system of claim 11 , wherein each sub-circuit stores a respective output pixel associated with convolving the input data and the second plurality of weights.
13 . The system of claim 11 , wherein an initial first vector of the individual first vectors is provided along a first direction of the matrix processor, and wherein an initial second vector of the individual second vectors is provided along a second direction of the matrix processor.
14 . The system of claim 13 , wherein the sub-circuits comprise respective multipliers, adders, and accumulators.
15 . The system of claim 14 , wherein accumulating partial dot products comprises:
determining first partial dot products based on respective values included in the initial first vector and the initial second vector, wherein the first partial dot products are stored in the sub-circuits; and
determining subsequent partial dot products based on respective values included in subsequent first vectors and subsequent second vectors,
wherein the sub-circuits are configured to add the first partial dot products stored in the accumulators with the subsequent partial dot products.
16 . The system of claim 11 , wherein the matrix processor comprises an array of tiles, and wherein the tiles comprise respective subsets of the sub-circuits.
17 . The system of claim 11 , wherein the input data comprises image data, LIDAR data, ultrasonic data, or radar data.
18 . A method implemented by a matrix processor, the method comprising:
receiving, from a first logic circuit, input data, wherein the input data is derived from convolving a first data and a first plurality of weights, and wherein the input data is organized into individual first vectors;
receiving, from a second logic circuit, a second plurality of weights, wherein the second plurality of weights are organized into individual second vectors; and
using a plurality of sub-circuits of the matrix processor to convolve the input data and the second plurality of weights for estimating the first data, wherein to convolve the input data and the second plurality of weights, the sub-circuits are configured to accumulate partial dot products associated with the individual first vectors and the individual second vectors.
19 . The method of claim 18 , wherein an initial first vector of the individual first vectors is provided along a first direction of the matrix processor, and wherein an initial second vector of the individual second vectors is provided along a second direction of the matrix processor.
20 . The method of claim 18 , wherein each sub-circuit stores a respective output pixel associated with convolving the input data and the second plurality of weights.