Granted Patent B2

US 12,431,890 · App. 18/328,251 · Granted Sep 30, 2025

Inventors: Tero Tapio Ranta (San Diego, CA); Shawn Bawell (Amherst, NH); Robert W. Greene (Lowell, MA); Christopher N. Brindle (Poway, CA); Robert Mark Englekirk (Littleton, CO)

Assignee: pSemi Corporation

H03K17/162H01F21/12H01G4/002H01G7/00H01L23/5223H03H7/0153H03H7/38H03H11/28H03J3/20H03K17/102H03K17/687H03M1/1061H10D1/692H10D84/811H10D86/201H03J2200/10H03M1/804

Abstract

Claims (38)

1. An integrated circuit comprising:

a series arrangement of three or more field-effect transistors (FET);

wherein:

i) the three or more FETs are configured to:

a) be connected in series with a series arrangement of one or more capacitive elements

b) receive a control signal to enable or disable the FETs thereby adjusting the capacitance between the two nodes,

ii) compensation capacitive elements are coupled across at least one of the three or more FETs, and

iii) a combination of the one or more capacitive elements and the three or more FETs is coupled between a first node and a second node.

2. The integrated circuit of claim 1 , wherein the at least one of the three or more FETs is closer to either the first node or the second node than the other of the first node or the second node.

3. The integrated circuit of claim 1 , wherein the three or more FETs are further configured to withstand a voltage greater than a voltage withstood by one FET of the three or more FETs.

4. The integrated circuit of claim 2 , wherein the compensation capacitive elements comprise metal-based capacitors.

5. The integrated circuit of claim 4 , wherein the metal-based capacitors comprise Metal-Metal (MM) capacitors.

6. The integrated circuit of claim 1 , wherein the compensation capacitive elements provide capacitance values that are symmetrical with reference to a node within the integrated circuit.

7. A digitally tuned capacitor (DTC) comprising a plurality of the integrated circuits of claim 6 , wherein the plurality of the integrated circuits are configured in parallel.

8. An integrated circuit comprising:

a series arrangement of two or more field-effect transistors (FET), wherein:

i) the two or more FETs are configured to be connected in series with a series arrangement of one or more capacitive elements to couple a combination of the one or more capacitive elements and the two or more FETs between a first node and a second node;

ii) each of the two or more FETs has a control node configured to receive a control signal via a resistive element to enable or disable the two or more FETs, and thereby adjusting the capacitance between the first node and the second node; and

iii) compensation capacitive elements are coupled across at least one of the two or more FETs.

9. The integrated circuit of claim 8 , wherein the two or more FETs are further configured to withstand a voltage greater than a voltage withstood by one FET of the two or more FETs.

10. The integrated circuit of claim 8 , wherein the compensation capacitive elements comprise metal-based capacitors.

11. The integrated circuit of claim 10 , wherein the metal-based capacitors comprise Metal-Metal (MM) capacitors.

12. The integrated circuit of claim 8 , wherein the compensation capacitive elements provide capacitance values that are symmetrical with reference to a node within the integrated circuit.

13. The integrated circuit of claim 8 , wherein the at least one of the two or more FETs is closer to either the first node or the second node than the other of the first node or the second node.

14. A digitally tuned capacitor (DTC) comprising a plurality of the integrated circuits of claims 13 , wherein the plurality of the integrated circuit are configured in parallel.

15. An integrated circuit comprising:

a series arrangement of one or more capacitive elements;

a series arrangement of a plurality of field-effect transistors (FET); and

a compensation capacitive element,

wherein:

the one or more capacitive elements are in series with the plurality of FETs;

a combination of the one or more capacitive elements and the plurality of FETs is coupled between a first node and a second node;

the plurality of FETs are configured to receive a control signal to enable or disable the FETs, thereby adjusting the capacitance between the two nodes, and

the compensation capacitive element is connected across one or more FETs of the plurality of FETs.

16. The integrated circuit of claim 15 , wherein the metal-based capacitor comprises a Metal-Metal (MM) capacitor.

17. The integrated circuit of claim 15 , wherein the plurality of FETs are further configured to withstand a voltage greater than a voltage withstood by one FET.

18. The integrated circuit of claim 15 , wherein the compensation capacitive element comprises a metal-based capacitor.

19. The integrated circuit of claim 18 , wherein the metal-based capacitor comprises a Metal-Insulator-Metal (MIM) capacitor.

Assignments (2)

Continuity (10)

References Cited (197)