Integrated circuit
A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.
1. An integrated circuit, comprising:
a metal/dielectric layer having a first dielectric layer and a conductive feature in the first dielectric layer;
a second dielectric layer over the metal/dielectric layer;
a bottom electrode over the conductive feature and surrounded by the second dielectric layer, wherein the bottom electrode has a sidewall landing on a tapered sidewall of the second dielectric layer;
a resistance switch element over the bottom electrode; and
a top electrode over the resistance switch element.
2. The integrated circuit of claim 1 , wherein a portion of the tapered sidewall of the second dielectric layer is free from coverage by the bottom electrode.
3. The integrated circuit of claim 1 , wherein the sidewall of the bottom electrode, a sidewall of the resistance switch element, and a sidewall of the top electrode are aligned with each other.
4. The integrated circuit of claim 1 , wherein the bottom electrode has a first portion, a second portion below the first portion, and a third portion over the first portion, and a width of the first portion of the bottom electrode is greater than a width of the second portion of the bottom electrode and a width of the third portion of the bottom electrode.
5. The integrated circuit of claim 4 , wherein the first portion of the bottom electrode is below a top surface of the second dielectric layer.
6. The integrated circuit of claim 1 , further comprising:
a spacer surrounding the top electrode and over the resistance switch element.
7. The integrated circuit of claim 1 , wherein the tapered sidewall of the second dielectric layer is curved.
8. The integrated circuit of claim 1 , wherein the second dielectric layer is a silicon carbide layer.
9. The integrated circuit of claim 1 , wherein an angle between the tapered sidewall of the second dielectric layer and a bottom surface of the second dielectric layer is in a range from 5 degrees to 75 degrees.
10. An integrated circuit, comprising:
a metal/dielectric layer having a first dielectric layer and a conductive feature in the first dielectric layer;
a second dielectric layer over the metal/dielectric layer;
a memory structure over the conductive feature and surrounded by the second dielectric layer, wherein the memory structure has a sidewall in contact with a tapered sidewall of the second dielectric layer;
an interlayer dielectric layer over the second dielectric layer and surrounding the memory structure; and
a top electrode in the interlayer dielectric layer and over the memory structure.
11. The integrated circuit of claim 10 , wherein the memory structure comprises a bottom electrode and a resistance switch element over the bottom electrode, the bottom electrode has a bottom portion, a middle portion, and a top portion, and the middle portion is wider than the bottom portion and the top portion.
12. The integrated circuit of claim 11 , wherein the middle portion of the bottom electrode has a greatest width at a position lower than a top surface of the second dielectric layer.
13. The integrated circuit of claim 10 , wherein the sidewall of the memory structure is slanted with respect to a top surface of the conductive feature.
14. The integrated circuit of claim 10 , wherein an angle between the sidewall of the memory structure and a top surface of the conductive feature is in a range from 30 degrees to 75 degrees.
15. An integrated circuit, comprising:
a metal/dielectric layer having a first dielectric layer and a conductive feature in the first dielectric layer;
a second dielectric layer over the metal/dielectric layer, wherein the second dielectric layer has a top surface and a tapered sidewall extending from the top surface to the conductive feature;
a bottom electrode over the conductive feature and in contact with the tapered sidewall of the second dielectric layer, wherein a top end of the tapered sidewall of the second dielectric layer is free from coverage by the bottom electrode;
a resistance switch element over the bottom electrode; and
a top electrode over the resistance switch element.
16. The integrated circuit of claim 15 , wherein a bottom end of the tapered sidewall of the second dielectric layer is covered by the bottom electrode.
17. The integrated circuit of claim 15 , wherein a top surface of the bottom electrode is higher than a top surface of the second dielectric layer.
18. The integrated circuit of claim 15 , wherein the top surface of the second dielectric layer is substantially parallel with the top surface to the conductive feature.
19. The integrated circuit of claim 15 , wherein the second dielectric layer comprises a material different from that of the first dielectric layer.
20. The integrated circuit of claim 15 , wherein the tapered sidewall of the second dielectric layer is curved.