Late SRAM cut with backside contact
A SRAM is provided that includes a first pull-up transistor having a first channel length, and a first pull-down transistor located adjacent to the first pull-up transistor and having a second channel length, wherein the second channel length is greater than the first channel length. The structure further includes a first backside contact structure contacting a first n-doped source/drain region of the first pull-down transistor, wherein the first backside contact structure has a first critical dimension that is constant throughout an entirety thereof, and a second backside contact structure having a vertical portion and a base portion. The vertical portion of the second backside contact structure directly contacts a first p-doped source/drain region of the first pull-up transistor and the base portion of the second backside contact structure has a second critical dimension that is greater than the first critical dimension.
1 . A static random access memory (SRAM) comprising:
a first pull-up transistor having a first channel length;
a first pull-down transistor located adjacent to the first pull-up transistor and having a second channel length, wherein the second channel length is greater than the first channel length;
a first backside contact structure contacting a first n-doped source/drain region of the first pull-down transistor, wherein the first backside contact structure has a first critical dimension that is constant throughout an entirety of the first backside contact structure; and
a second backside contact structure having a vertical portion and a base portion, wherein the vertical portion of the second backside contact structure directly contacts a first p-doped source/drain region of the first pull-up transistor and the base portion of the second backside contact structure has a second critical dimension that is greater than the first critical dimension.
2 . The SRAM of claim 1 , wherein the vertical portion of the second backside contact structure has a third critical dimension, wherein the third critical dimension is less than both the first critical dimension and the second critical dimension.
3 . The SRAM of claim 1 , wherein the n-doped source/drain region of the first pull-down transistor is confined between a pair of dielectric spacers.
4 . The SRAM of claim 1 , wherein the p-doped source/drain region of the first pull-up transistor is confined on a first side by a dielectric spacer and on a second side by a double diffusion break structure.
5 . The SRAM of claim 4 , wherein the double diffusion break structure directly contacts a surface of the base portion of the second backside contact structure.
6 . The SRAM of claim 1 , wherein the first pull-down transistor is located in a first active area and the first pull-up transistor is located in a second active area, wherein the first active area and the second active area are separated by a shallow trench isolation structure.
7 . The SRAM of claim 6 , further comprising a second pull-up transistor located in the second active area, wherein the first pull-up transistor and the second pull-up transistor are both located on a bottom dielectric isolation layer that extends continuously beneath the first pull-up transistor and the second pull-up transistor.
8 . The SRAM of claim 1 , wherein the base portion of the second backside contact structure directly contacts a first surface of a VDD power supply.
9 . The SRAM of claim 8 , wherein the VDD power supply has a second surface opposite the first surface of the VDD power supply directly contacting a backside power distribution network.
10 . The SRAM of claim 9 , wherein the first backside contact structure directly contacts a first surface of a VSS power supply.
11 . The SRAM of claim 10 , wherein the VSS power supply has a second surface opposite the first surface of the VSS power supply directly contacting the backside power distribution network.
12 . The SRAM of claim 1 , wherein the first pull-up transistor has a gate structure, wherein the gate structure of the first pull-up transistor is electrically connected to a second p-doped source/drain region of the first pull-up transistor by a cross-couple (XC) frontside contact structure.
13 . The SRAM of claim 12 , wherein the XC frontside contact structure contacts a frontside back-end-of-the-line (BEOL) structure.
14 . The SRAM of claim 13 , wherein the first pull-down transistor has a gate structure, wherein the gate structure of the first pull-down transistor is electrically connected to the frontside BEOL structure by a frontside gate contact structure.
15 . A semiconductor structure comprising:
a p-type nanosheet transistor having a first channel length;
an n-type nanosheet transistor located adjacent to the p-type nanosheet transistor and having a second channel length, wherein the second channel length is greater than the first channel length;
a first backside contact structure contacting an n-doped source/drain region of the n-type nanosheet transistor, wherein the first backside contact structure has a first critical dimension that is constant throughout an entirety of the first backside contact structure;
a second backside contact structure having a vertical portion and a base portion, wherein the vertical portion of the second backside contact structure directly contacts a p-doped source/drain region of the p-type nanosheet transistor and the base portion of the second backside contact structure has a second critical dimension that is greater than the first critical dimension.
16 . The semiconductor structure of claim 15 , wherein the vertical portion of the second backside contact structure has a third critical dimension, wherein the third critical dimension is less than both the first critical dimension and the second critical dimension.
17 . The semiconductor structure of claim 15 , wherein the n-doped source/drain region of the n-type nanosheet transistor is confined on a first side by a dielectric spacer and on a second side by a double diffusion break structure.
18 . The semiconductor structure of claim 17 , wherein the double diffusion break structure directly contacts a surface of the base portion of the second backside contact structure.
19 . The semiconductor structure of claim 15 , wherein the base portion of the second backside contact structure directly contacts a first surface of a VDD power supply, and wherein a second surface of the VDD power supply that is opposite the first surface of the VDD power supply directly contacts a backside power distribution network, and wherein the first backside contact structure directly contacts a first surface of a VSS power supply and a second surface of the VSS power supply opposite the first surface of the VSS power supply directly contacts the backside power distribution network.
20 . The semiconductor structure of claim 15 , wherein the p-type nanosheet transistor has a gate structure, wherein the gate structure of the n-type nanosheet transistor is electrically connected to a second p-doped source/drain region of the n-type nanosheet transistor by a cross-couple (XC) frontside contact structure, and the XC frontside contact structure further contacts a frontside BEOL structure, and wherein the n-type nanosheet transistor is electrically connected to the frontside BEOL structure by a frontside gate contact structure.