Backside diffusion break
A semiconductor integrated circuit (IC) device includes a diffusion break region that has a diffusion break dielectric adjacent to or between diffusion break isolation wall(s). The diffusion break region may separate adjacent transistors. The diffusion break isolation wall(s) may include respective retained portions of a backside spacer, a bottom isolation, respective inner spacers, and residual active semiconductor nanolayers. The diffusion break region may be fabricated by depositing a diffusion break dielectric within a diffusion break opening against the diffusion break isolation wall(s).
1 . A semiconductor integrated circuit (IC) device comprising:
a first diffusion break isolation wall comprising a first backside spacer, a first bottom isolation region directly upon the first backside spacer, a first alternating series of residual nanolayer channel layers and residual inner spacers directly upon the first bottom isolation region, and a first gate spacer directly upon the first alternating series of residual nanolayer channel layers and residual inner spacers; and
a diffusion break dielectric directly against an outer sidewall of the first diffusion break isolation wall.
2 . The semiconductor IC device of claim 1 , wherein the first backside spacer is directly against a sidewall of a backside contact placeholder.
3 . The semiconductor IC device of claim 2 , wherein a bottom surface of the first backside spacer is substantially coplanar with a bottom surface of the backside contact placeholder.
4 . The semiconductor IC device of claim 3 , wherein an inner sidewall of the first diffusion break isolation wall is directly against a sidewall of a source/drain (S/D) region.
5 . The semiconductor IC device of claim 1 , wherein a bottom surface of the S/D region is directly against a top surface of the backside contact placeholder.
6 . The semiconductor IC device of claim 5 , wherein charge carriers do not flow through the residual nanolayer channel layers.
7 . The semiconductor IC device of claim 6 , further comprising:
a frontside interlayer dielectric (ILD) upon the S/D region, upon the first gate spacer, and upon the diffusion break dielectric; and
a backside ILD upon the backside contact placeholder, upon the first backside spacer, and upon the diffusion break dielectric.
8 . The semiconductor IC device of claim 7 , wherein the backside ILD and the diffusion break dielectric are composed of a same first dielectric material.
9 . The semiconductor IC device of claim 8 , wherein the frontside ILD is composed of a second dielectric material different from the first dielectric material.
10 . The semiconductor IC device of claim 1 , further comprising:
a second diffusion break isolation wall comprising a second backside spacer, a second bottom isolation region directly upon the second backside spacer, a second alternating series of residual nanolayer channel layers and residual inner spacers directly upon the second bottom isolation region, and a second gate spacer directly upon the alternating series of residual nanolayer channel layers and residual inner spacers; and
wherein the diffusion break dielectric is further directly against an outer sidewall of the second diffusion break isolation wall.
11 . The semiconductor IC device of claim 10 , wherein a dimension between a bottom surface of the first backside spacer and a bottom surface of the second backside spacer is substantially the same as a dimension between a top surface of the first gate spacer and a top surface of the second gate spacer.
12 . The semiconductor IC device of claim 1 , wherein the first backside spacer is directly against a sidewall of a backside contact.
13 . A semiconductor integrated circuit (IC) device comprising:
a first diffusion break isolation wall comprising a first backside spacer, a first alternating series of residual nanolayer channel layers and residual inner spacers directly upon the backside spacer, and a first gate spacer directly upon the first alternating series of residual nanolayer channel layers and residual inner spacers; and
a diffusion break dielectric directly against an outer sidewall of the first diffusion break isolation wall.
14 . The semiconductor IC device of claim 13 , wherein the first backside spacer is directly against a sidewall of a backside contact placeholder.
15 . The semiconductor IC device of claim 14 , wherein a bottom surface of the first backside spacer is substantially coplanar with a bottom surface of the backside contact placeholder.
16 . The semiconductor IC device of claim 15 , wherein an inner sidewall of the first diffusion break isolation wall is directly against a sidewall of a source/drain (S/D) region.
17 . The semiconductor IC device of claim 13 , further comprising:
a second diffusion break isolation wall comprising a second backside spacer, a second alternating series of residual nanolayer channel layers and residual inner spacers directly upon second backside spacer, and a second gate spacer directly upon the alternating series of residual nanolayer channel layers and residual inner spacers;
and wherein the diffusion break dielectric is further directly against an outer sidewall of the second diffusion break isolation wall.
18 . The semiconductor IC device of claim 17 , wherein a dimension between a bottom surface of the first backside spacer and a bottom surface of the second backside spacer is substantially the same as a dimension between a top surface of the first gate spacer and a top surface of the second gate spacer.
19 . The semiconductor IC device of claim 17 , wherein a dimension between a bottom surface of the first backside spacer and a bottom surface of the second backside spacer is greater than a dimension between a top surface of the first gate spacer and a top surface of the second gate spacer.