Methods of forming semiconductor device structures
View Patent ↗Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming an interconnect structure over a substrate. The forming the interconnect structure over the semiconductor device structure includes forming a dielectric layer, then performing an annealing process, then forming one or more openings in the dielectric layer, then performing a first ultraviolet (UV) curing process, and then forming conductive features in the one or more openings.
1 . A method, comprising:
forming an interconnect structure over a substrate, comprising:
forming a dielectric layer;
forming an opening in the dielectric layer;
forming a conductive feature in the opening;
forming a cap layer on the conductive feature, wherein the cap layer comprises a metal and is formed by a plasma enhanced chemical vapor deposition process; and then
performing a first ultraviolet (UV) curing process immediately after forming the cap layer, wherein electric charge accumulated on the dielectric layer as a result of the plasma enhanced chemical vapor deposition process is removed by the first UV curing process.
2 . The method of claim 1 , wherein the first UV curing process comprises exposing the cap layer to a first UV light having a wavelength ranging from about 200 nm to about 400 nm.
3 . The method of claim 2 , wherein a processing temperature of the first UV curing process ranges from about 70 degrees Celsius to about 400 degrees Celsius.
4 . The method of claim 3 , wherein a processing pressure of the first UV curing process ranges from about 1 Torr to about 10 Torr.
5 . The method of claim 1 , wherein the opening is formed by a dry etch process or a wet etch process.
6 . The method of claim 5 , further comprising performing a second UV curing process after forming the opening in the dielectric layer.
7 . The method of claim 6 , wherein the second UV curing process comprises exposing the dielectric layer to a second UV light having a wavelength ranging from about 200 nm to about 400 nm.
8 . The method of claim 1 , wherein the cap layer comprises cobalt.
9 . A method, comprising:
forming a semiconductor fin;
forming an insulating structure to embed the semiconductor fin;
performing an annealing process;
recessing the insulating structure to form a shallow trench isolation (STI) region, wherein the recessing the insulating structure is performed by a wet etch process; then
performing a first ultraviolet (UV) curing process on the STI region; and
forming a sacrificial gate structure over the semiconductor fin.
10 . The method of claim 9 , wherein the first UV curing process comprises exposing the STI region to an UV light having a wavelength ranging from about 200 nm to about 400 nm.
11 . The method of claim 10 , wherein a processing temperature of the first UV curing process ranges from about 70 degrees Celsius to about 400 degrees Celsius.
12 . The method of claim 11 , wherein a processing pressure of the first UV curing process ranges from about 1 Torr to about 10 Torr.
13 . The method of claim 9 , wherein the forming the sacrificial gate structure comprises:
forming a sacrificial gate dielectric layer;
forming a sacrificial gate electrode layer; and
removing portions of the sacrificial gate dielectric layer and portions of the sacrificial gate electrode layer to expose portions of the STI region.
14 . The method of claim 13 , further comprising performing a second UV curing process after exposing the portions of the STI region.
15 . The method of claim 14 , further comprising recessing portions of the semiconductor fin not covered by the sacrificial gate structure.
16 . The method of claim 15 , further comprising performing a third UV curing process after the recessing the portions of the semiconductor fin not covered by the sacrificial gate structure.
17 . A method, comprising:
forming an insulating structure over a substrate;
recessing the insulating structure;
performing a first ultraviolet (UV) curing process;
forming source/drain epitaxial features over the substrate;
forming a gate electrode layer over the substrate;
forming a dielectric layer over the source/drain epitaxial features and the gate electrode layer;
forming an opening in the dielectric layer;
performing a second UV curing process;
forming a conductive feature in the opening;
forming a cap layer on the conductive feature by a plasma enhanced chemical vapor deposition process, wherein the cap layer comprises a metal; and
performing a third UV curing process immediately after forming the cap layer, wherein electric charge accumulated on the dielectric layer as a result of the plasma enhanced chemical vapor deposition process is removed by the third UV curing process.
18 . The method of claim 17 , wherein the first UV curing process comprises exposing the insulating structure to an UV light having a wavelength ranging from about 200 nm to about 400 nm.
19 . The method of claim 17 , wherein the second UV curing process is performed to remove electric charge accumulated on the dielectric layer.
20 . The method of claim 17 , wherein the cap layer comprises cobalt.