Error correction for identifier data generated from unclonable characteristics of resistive memory
Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be referred to as physical unclonable feature—or function—(PUF) data. Additionally, error correction functions for PUF data generated from resistive switching memory cells are provided. The error correction functions facilitate additional redundancy and longevity of PUF data, among other benefits. Different embodiments include addressing arrangements to incorporate ECC parity bits among generated PUF data bits, even for differential PUF bits respectively defined by multiple memory cells in different portions of a resistive memory array.
1 . An integrated circuit device, comprising:
a resistive switching memory array comprising a plurality of resistive switching devices disposed overlying a substrate;
a control circuit for segregating a subset of the plurality of resistive switching devices thereby defining a first subset of the resistive switching devices;
an error correction control (ECC) encoder configured to generate correction data for data at the resistive switching memory array; and
a sensing circuit disposed at least in part on the substrate and electrically coupled to the plurality of resistive switching devices, wherein the sensing circuit is configured to selectively apply a sense signal to a first resistive switching device of the first subset of the resistive switching devices, wherein the sensing circuit is configured to determine a first response signal from the first resistive switching device in response to the sense signal, and wherein the sensing circuit is configured to selectively apply the sense signal to a second resistive switching device of the first subset of the resistive switching devices, wherein the sensing circuit is configured to determine a second response signal from the second resistive switching device in response to the sense signal, wherein:
the control circuit defines a bit for the combination of the first resistive switching device and the second resistive switching device,
the control circuit establishes a logic value for the bit based on the first response signal and second response signal,
the control circuit establishes additional logic values for additional bits defined for respective additional pairs of the first subset of the resistive switching devices, the respective additional pairs excluding the first resistive switching device or excluding the second resistive switching device, and the bit and the additional bits defining a sequence of data, and
the ECC encoder generates error correction data corresponding to the sequence of data.
2 . The integrated circuit device of claim 1 , wherein each of the plurality of resistive switching devices is associated with an operational programming characteristic having low correlation among resistive switching devices of the plurality of resistive switching devices and wherein the low correlation is defined by a correlation coefficient within a range of about −0.1 to about 0.1.
3 . The integrated circuit device of claim 1 , further comprising a command and data interface for receiving a command from a host device specifying an address associated with the plurality of resistive switching devices, and specifying a command causing the control circuit to select the first subset of the resistive switching devices from the address.
4 . The integrated circuit device of claim 1 , wherein the sensing circuit is configured to read the sequence of data and provide the sequence of data to the ECC encoder to generate the error correction data.
5 . The integrated circuit device of claim 1 , wherein the control circuit is configured to at least one of:
apply a strong program pulse to the first resistive switching device in response to the first response signal being a program response; or
apply the strong program pulse to the second resistive switching device in response to the second response signal being the program response.