Microelectronic device assemblies, stacked semiconductor die assemblies, and memory device packages
Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.
1 . A microelectronic device assembly, comprising:
a substrate having conductive pads at an upper surface thereof;
a first non-conductive polymer material on the upper surface of the substrate;
a first semiconductor die on the first non-conductive polymer material;
redistribution layer (RDL) pads at a bottom surface of the first semiconductor die opposing the upper surface of the substrate; and
first conductive contacts coupled to the RDL pads and vertically extending to the substrate, some of the first conductive contacts physically contacting the conductive pads;
second conductive contacts coupled to the RDL pads and vertically extending completely through first semiconductor material of the first semiconductor die;
a second semiconductor die overlying the first semiconductor die;
a second non-conductive polymer material vertically interposed between the first semiconductor die and the second semiconductor die;
third conductive contacts vertically extending completely through second semiconductor material of the second semiconductor die, the third conductive contacts horizontally overlapping the second conductive contacts; and
fourth conductive contacts vertically extending through the second non-conductive polymer material and coupled to the third conductive contacts and the second conductive contacts.
2 . The microelectronic device assembly of claim 1 , further comprising:
additional conductive contacts coupled to the conductive pads and vertically extending completely through the substrate; and
solder balls on a lower surface of the substrate, some of the additional conductive contacts vertically extending to and in physical contact with some of the solder balls.
3 . The microelectronic device assembly of claim 1 , wherein RDL pads comprise copper.
4 . The microelectronic device assembly of claim 1 , wherein the first non-conductive polymer material physically contacts each of the bottom surface of the first semiconductor die and side surfaces of the first semiconductor die.
5 . The microelectronic device assembly of claim 1 , further comprising an epoxy molding compound (EMC) on the upper surface of the substrate and enveloping the first non-conductive polymer material, the first semiconductor die, the second non-conductive polymer material, and the second semiconductor die.
6 . A stacked semiconductor die assembly, comprising:
a substrate having first conductive pads at an upper surface thereof;
a die stack vertically overlying the substrate and comprising:
a first non-conductive film (NCF) material on the upper surface of the substrate;
a first semiconductor die on the first NCF material, the first NCF material covering a bottom surface and side surfaces of the first semiconductor die;
a second NCF material over an upper surface of the first semiconductor die; and
a second semiconductor die on the second NCF material, the second NCF material covering a bottom surface and side surfaces of the second semiconductor die; and
first conductive contacts vertically extending through the first NCF material and the second NCF material of the die stack to the first conductive pads at the upper surface of the substrate, the first conductive contacts respectively offset from horizontal areas of the first semiconductor die and the second semiconductor die of the die stack.
7 . The stacked semiconductor die assembly of claim 6 , wherein the die stack further comprises:
first conductive traces coupled to the first semiconductor die and the first conductive contacts, respective ones of the first conductive traces horizontally extending from the first semiconductor die to respective ones of the first conductive contacts; and
second conductive traces coupled to the second semiconductor die and the first conductive contacts, respective ones of the second conductive traces horizontally extending from the second semiconductor die to the respective ones of the first conductive contacts.
8 . The stacked semiconductor die assembly of claim 7 , wherein the die stack further comprises:
a first fan-out-package-(FOP)-configured redistribution layer (RDL) vertically interposed between the first semiconductor die and the second NCF material and bearing the first conductive traces; and
a second FOP-configured RDL vertically overlying the second semiconductor die and bearing the second conductive traces.
9 . The stacked semiconductor die assembly of claim 8 , wherein:
the first FOP-configured RDL comprises first inductive coupling loop (ICP) transmitters and first ICP receivers coupled to first date signal pinouts of the first semiconductor die; and
the second FOP-configured RDL comprises second ICP transmitters and second ICP receivers coupled to second date signal pinouts of the second semiconductor die.
10 . The stacked semiconductor die assembly of claim 6 , further comprising:
second conductive pads at the upper surface of the substrate and coupled to conductive structures at a bottom surface of the substrate; and
second conductive contacts on the first conductive pads and vertically extending through the first NCF material to the first semiconductor die.
11 . The stacked semiconductor die assembly of claim 10 , wherein the second conductive contacts are directly attached to the second conductive pads by way of thermocompression bonds.
12 . The stacked semiconductor die assembly of claim 6 , further comprising decoupling capacitors respectively coupled to one or more of the first conductive contacts, the decoupling capacitors offset from the horizontal areas of the first semiconductor die and the second semiconductor die of the die stack.
13 . A memory device package, comprising:
a substrate;
a die stack vertically overlying and operably coupled to the substrate, the die stack comprising:
memory levels respectively comprising at least one memory die;
non-conductive polymer material vertically alternating with the memory levels; and
adhesive material on a bottom surface of the at least one memory die of respective ones of the memory levels, the adhesive material having a different material composition than the non-conductive polymer material; and
conductive contacts operably coupled to circuitry of at least some of the memory levels and additional circuitry of the substrate, the conductive contacts vertically extending through portions of the non-conductive polymer material extending beyond lateral peripheries of the at least one memory die of respective ones of the memory levels.
14 . A memory device package, comprising:
a substrate;
a die stack vertically overlying and operably coupled to the substrate, the die stack comprising:
memory levels respectively comprising at least one memory die, the at least one memory die of a vertically lowest one of the memory levels of the die stack operably coupled to the substrate through a direct-chip-attach (DCA) assembly comprising:
conductive pads at a bottom surface of the at least one memory die; and
additional conductive contacts coupled to the conductive pads and vertically extending to the substrate; and
non-conductive polymer material vertically alternating with the memory levels; and
conductive contacts operably coupled to circuitry of at least some of the memory levels and additional circuitry of the substrate, the conductive contacts vertically extending through portions of the non-conductive polymer material extending beyond lateral peripheries of the at least one memory die of respective ones of the memory levels.
15 . The memory device package of claim 13 , wherein the non-conductive polymer material comprises one or more of silica-filled epoxy, b-staged polyimide, and polytetrafluoroethylene.
16 . The memory device package of claim 13 , wherein the die stack further comprises a controller die vertically overlying an uppermost one of the memory levels.