Integrated circuit package for scan testing semiconductor chip, operating method of integrated circuit package, and integrated circuit
An integrated circuit package for scan testing a semiconductor chip includes at least one first input pad configured to receive a first input signal, at least one chip connected to the first input pad, and at least one first output pad configured to receive a first output signal generated by the at least one chip, wherein each of the at least one chip includes at least one second input pad configured to receive a second input signal, a plurality of scan chains, a first test circuit and a second test circuit, which share the plurality of scan chains, and at least one second output pad configured to receive a second output signal from the first test circuit.
1. An integrated circuit package for scan testing a semiconductor chip, the integrated circuit package comprising:
at least one first input pad configured to receive a first input signal;
at least one chip connected to the at least one first input pad; and
at least one first output pad configured to receive a first output signal generated from the at least one chip, wherein
each of the at least one chip comprises
at least one second input pad configured to receive a second input signal;
a plurality of scan chains;
a first test circuit and a second test circuit sharing the plurality of scan chains; and
at least one second output pad configured to receive a second output signal from the first test circuit, wherein
the integrated circuit package comprises
a signal selection circuit configured to receive a selection signal and determine whether the first input signal is used in the first test circuit or the second test circuit, based on the selection signal.
2. The integrated circuit package of claim 1 , wherein
the signal selection circuit further comprises a third input pad configured to receive the selection signal, and
the signal selection circuit is configured to selectively provide the first input signal to the second test circuit based on the selection signal.
3. The integrated circuit package of claim 2 , wherein the signal selection circuit is configured to selectively provide the first input signal to the first test circuit based on the selection signal.
4. The integrated circuit package of claim 2 , wherein each of the at least one chip further comprises an output selection circuit configured to receive the first output signal and the second output signal.
5. The integrated circuit package of claim 4 , wherein, when the first input signal is input to the first test circuit, the output selection circuit outputs the first output signal to the first output pad.
6. The integrated circuit package of claim 4 , wherein, when the second input signal is input to the first test circuit, the first test circuit is configured to output the first output signal to the second output pad.
7. The integrated circuit package of claim 4 , wherein, when the first input signal is input to the second test circuit, the output selection circuit is configured to output the second output signal to the first output pad.
8. The integrated circuit package of claim 1 , wherein
the first input pad and the first output pad are exposed to outside of the integrated circuit package, and
the second input pad and the second output pad are exposed to a plurality of terminals outside the at least one chip and inside the integrated circuit package.
9. An operating method of an integrated circuit package for scan testing a semiconductor chip, the operating method comprising:
receiving a first input signal through a first input pad;
receiving a selection signal by a selection signal circuit;
determining, based on the selection signal, whether the first input signal is provided to one of a first test circuit and a second test circuit of at least one chip exposed to the semiconductor chip; and
outputting a first output signal generated by the first test circuit or a second output signal generated by the second test circuit, wherein
the outputting the first output signal or the second output signal comprises,
when the first input signal is input to the first test circuit, outputting the first output signal to a first output pad exposed to outside of the semiconductor chip.
10. The operating method of claim 9 , further comprising:
inputting a second input signal to a second input pad exposed to outside of the first test circuit and inside of the semiconductor chip.
11. The operating method of claim 9 , wherein the determining of whether the first input signal is provided to one of the first test circuit and the second test circuit comprises providing the first input signal to the second test circuit when a logic value of the selection signal is in a low state.
12. The operating method of claim 9 , wherein the determining of whether the first input signal is provided to one of the first test circuit and the second test circuit comprises providing the first input signal to the first test circuit when a logic value of the selection signal is in a high state.
13. The operating method of claim 9 , further comprising:
determining whether to output the first output signal and the second output signal.
14. The operating method of claim 13 , wherein the outputting the first output signal or the second output signal comprises outputting the second output signal to the first output pad when the first input signal is input to the second test circuit.
15. An integrated circuit for scan testing a semiconductor chip, the integrated circuit comprising:
a first test circuit configured to receive one of a first input signal and a second input signal, and generate a first output signal;
a second test circuit configured to receive the first input signal and generate a second output signal, wherein
the first test circuit comprises
a first decompressor configured to receive the first input signal or the second input signal,
a first compressor configured to generate the first output signal, and
a scan chain configured to connect the first decompressor with the first compressor, and
the second test circuit comprises
a second decompressor configured to receive the first input signal,
a second compressor configured to generate the second output signal, and
the scan chain configured to connect the second decompressor with the second compressor,
a signal selection circuit configured to determine whether the first input signal or the second input signal is used in the first test circuit, based on a selection signal, and
an output selection circuit configured to receive the first output signal from the first compressor and the second output signal from the second compressor, and output one of the first output signal and the second output signal based on the selection signal.
16. The integrated circuit of claim 15 , wherein, when a logic value of the selection signal is in a high state and the first input signal is received, the output selection circuit is configured to output the first output signal to a first output pad exposed to outside of the integrated circuit.
17. The integrated circuit of claim 15 , wherein, when a logic value of the selection signal is in a low state, the signal selection circuit is configured to provide the first input signal to the second test circuit.
18. The integrated circuit of claim 15 , wherein, when a logic value of the selection signal is in a low state and the first input signal is received, the second test circuit is configured to output the second output signal to a first output pad exposed to outside of the integrated circuit.
19. The integrated circuit of claim 15 , wherein, when the second input signal is received by the first test circuit, the first test circuit is configured to output the first output signal to a second output pad exposed to outside of the integrated circuit.