Instruction set architecture for a vector computational unit
A microprocessor system comprises a vector computational unit and a control unit. The vector computational unit includes a plurality of processing elements. The control unit is configured to provide at least a single processor instruction to the vector computational unit. The single processor instruction specifies a plurality of component instructions to be executed by the vector computational unit in response to the single processor instruction and each of the plurality of processing elements of the vector computational unit is configured to process different data elements in parallel with other processing elements in response to the single processor instruction.
1. A microprocessor system, comprising:
a vector computational unit that includes a plurality of processing elements, wherein each processing element is connected to a corresponding computation unit in a last row of a plurality of computation units included in a computational array and each processing element is connected to a memory,
wherein information associated with a row of data elements is provided in parallel to the plurality of processing elements by the computational array and the memory; and
a control unit circuit configured to provide at least a processor instruction to the vector computational unit, the control unit circuit being configured to synchronize receipt of the information from the computational array and the memory to respective processing elements,
wherein each of the plurality of processing elements of the vector computational unit is configured to process the information in response to the processor instruction,
wherein the processor instruction specifies at least a register in the memory, and wherein one or more processing elements of the plurality of processing elements load the information from the register.
2. The microprocessor system of claim 1 , wherein each computation unit included in the computational array is configured to receive a weight input and a data input.
3. The microprocessor system of claim 1 , wherein for a particular clock cycle of the vector computational unit, a load operation associated with a first component instruction of the processor instruction, an arithmetic logic unit operation associated with a second component instruction of the processor instruction, and a store operation associated with a third component instruction of the processor instruction, are executed in parallel.
4. The microprocessor system of claim 1 , wherein the vector computational unit is configured to perform one or more non-linear functions on the information.
5. The microprocessor system of claim 1 , further comprising a post-processing unit, the post-processing unit configured to receive processed information from the vector computational unit.
6. The microprocessor system of claim 5 , wherein the post-processing unit is further configured to perform pooling operations on the processed information.
7. The microprocessor system of claim 5 , wherein the post-processing unit is further configured to format and store the processed information in the memory.
8. The microprocessor system of claim 1 , wherein the vector computational unit is configured to receive one or more input weights from the memory.
9. The microprocessor system of claim 1 , wherein the processor instruction comprises a memory access operation component instruction and an arithmetic logic unit operation component instruction.
10. The microprocessor system of claim 1 , wherein based on the last row of the computation units being configured to dequeue the row of data elements, a dequeue ready signal is received by the vector computational unit to indicate that the computational array is configured to receive a queue operation.
11. A method comprising:
receiving a processor instruction from a control unit circuit;
decoding the processor instruction;
using a vector computational unit that includes a plurality of processing elements to execute the decoded processor instruction, the processing elements being connected to a corresponding computation unit in a last row of a plurality of computation units included in a computational array, and the processing elements being connected to a memory;
wherein information associated with a row of data elements is provided in parallel to the plurality of processing elements by the computational array and the memory;
wherein the processor instruction specifies at least a register in the memory, wherein one or more processing elements of the plurality of processing elements load the information from the register; and
using each of the plurality of processing elements to process the information,
wherein the control unit circuit is configured to synchronize receipt of the data elements from the computational array and the memory to respective processing elements.
12. The method of claim 11 , wherein each computation unit included in the computational array is configured to receive a weight input and a data input.
13. The method of claim 11 , wherein for a particular clock cycle of the vector computational unit, a load operation associated with a first component instruction of the processor instruction, an arithmetic logic unit operation associated with a second component instruction of the processor instruction, and a store operation associated with a third component instruction of the processor instruction, are executed in parallel.
14. The method of claim 11 , wherein the vector computational unit is configured to perform one or more non-linear functions on the information.
15. The method of claim 11 , further comprising using a post-processing unit on processed information from the vector computational unit.
16. The method of claim 15 , wherein using the post-processing unit comprises perform pooling operations on the processed information.
17. The method of claim 15 , wherein using the post-processing unit comprises formatting and storing the processed information in the memory.
18. The method of claim 11 , wherein the vector computational unit is configured to receive one or more input weights from the memory.
19. The method of claim 11 , wherein the decoded processor instruction comprises a memory access operation component instruction and an arithmetic logic unit operation component instruction.
20. The method of claim 11 , wherein based on the last row of the computation units being configured to dequeue the row of data elements, a dequeue ready signal is received by the vector computational unit to indicate that the computational array is configured to receive a queue operation.