IP Library › Granted Patent US 12,348,883
Granted Patent B2
US 12,348,883 · App. 18/497,512 · Granted Jul 1, 2025

Imaging element

Inventors: Toshiyuki Nishihara (Kanagawa, JP); Tomohiro Takahashi (Tokyo, JP); Masao Matsumura (Kanagawa, JP); Tsutomu Imoto (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H04N25/616H04N25/60H04N25/70H04N25/75H04N25/76H04N25/77H04N25/771H04N25/79H10F39/12H10F39/809
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Quick Facts
Patent No.
US 12,348,883
App. No.
18/497,512
Granted
Jul 1, 2025
Kind
B2
Abstract

The present technology relates to an imaging element that can reduce noise. The imaging element includes: a photoelectric conversion element; a first amplification element that amplifies a signal from the photoelectric conversion element; a second amplification element that amplifies an output from the first amplification element; an offset element provided between the first amplification element and the second amplification element; a first reset element that resets the first amplification element; and a second reset element that resets the second amplification element. The offset element is a capacitor. A charge is accumulated in the offset element via a feedback loop of an output from the second amplification element, and an offset bias is generated. The present technology can be applied to an imaging element.

Claims (42)

1. A light detecting device, comprising:

a photoelectric conversion element connected to a transfer transistor;

a first amplification element, wherein a gate of the first amplification element is connected to a first detection node;

a second amplification element, wherein a gate of the second amplification element is connected to a second detection node;

a capacitor element provided between the first amplification element and the second amplification element;

a first reset element, wherein a gate of the first reset element is connected to a circuit; and

a first transistor, wherein a gate of the first transistor is connected to the circuit.

2. The light detecting device according to claim 1 , wherein the photoelectric conversion element is connected to the transfer transistor via an accumulation node.

3. The light detecting device according to claim 1 , wherein a charge is accumulated in the capacitor element via a feedback loop of an output from the second amplification element, and an offset bias is generated.

4. The light detecting device according to claim 2 , wherein the accumulation node is a cathode.

5. The light detecting device according to claim 1 , wherein a drain of the first amplification element and a drain of the second amplification element are connected to a power supply.

6. The light detecting device according to claim 1 , further comprising:

a differential amplifier, wherein an output signal from the second amplification element and a reference signal are input to the differential amplifier, and wherein an output from the differential amplifier is supplied to the first transistor.

7. The light detecting device according to claim 6 , wherein the differential amplifier includes the first transistor and a current mirror circuit.

8. The light detecting device according to claim 1 , wherein an input parasitic capacitance of the second amplification element is larger than an input parasitic capacitance of the first amplification element.

9. The light detecting device according to claim 1 , wherein after the first amplification element is reset by the first reset element, the second amplification element is reset by the first transistor.

10. The light detecting device according to claim 1 , wherein charge transfer and resetting of the photoelectric conversion element are performed in a same period.

11. The light detecting device according to claim 1 , wherein the second detection node performs sampling of each of a reset signal and an accumulated signal, including processing of correlated double sampling.

12. The light detecting device according to claim 11 ,

wherein the second detection node considers a predetermined row as a processing target and performs sampling of a reset signal from the predetermined row, and

wherein the second detection node performs sampling of accumulated signals from all rows including the predetermined row.

13. The light detecting device according to claim 1 , wherein the second detection node does not perform sampling of a reset signal and only performs sampling of an accumulated signal, including processing of correlated double sampling.

14. The light detecting device according to claim 1 ,

wherein the photoelectric conversion element, the first amplification element, and the first reset element are formed in a first layer,

wherein the capacitor element, the second amplification element, and the first transistor are formed in a second layer, and

wherein the first layer and the second layer are stacked.

15. The light detecting device according to claim 14 ,

wherein the second detection node detects a signal from the second amplification element and is formed in a third layer, and

wherein the first layer, the second layer, and the third layer are stacked.

16. The light detecting device according to claim 1 , wherein a source of the second amplification element is connected to a second load transistor.

17. The light detecting device according to claim 1 , wherein a source of the first reset element is connected to a first load transistor.

18. An imaging element, comprising:

a plurality of pixels, wherein each pixel includes:

a photoelectric conversion element connected to a transfer transistor;

a first amplification element, wherein a gate of the first amplification element is connected to a first detection node;

a second amplification element wherein a gate of the second amplification element is connected to a second detection node;

a capacitor element provided between the first amplification element and the second amplification element;

a first reset element, wherein a gate of the first reset element is connected to a row drive circuit; and

a first transistor, wherein a gate of the first transistor is connected to the row drive circuit.

19. The imaging element according to claim 18 , wherein the photoelectric conversion element is connected to the transfer transistor via an accumulation node.

20. The imaging element according to claim 18 , further comprising:

a differential amplifier, wherein an output signal from the second amplification element and a reference signal are input to the differential amplifier, and wherein an output from the differential amplifier is supplied to the first transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2023
From: NISHIHARA, TOSHIYUKI; TAKAHASHI, TOMOHIRO; MATSUMURA, MASAO; IMOTO, TSUTOMU
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 065390/0647 →
Priority Claims (1)
JP 2016-147994 · Jul 28, 2016 · national
Continuity (5)
Continuation 18124410 · Mar 21, 2023
Continuation 17863279 · Jul 12, 2022
Continuation 16996745 · Aug 18, 2020
Continuation 16318650
Related Publication 20240064425A1 · Feb 22, 2024
References Cited (25)
US 9153619B2 · Kurokawa · 2015 [cited by examiner]
US 9667898B2 · Vogelsang · 2017 [cited by examiner]
US 10771719B2 · Nishihara et al. · 2020 [cited by applicant]
US 11431927B2 · Nishihara et al. · 2022 [cited by applicant]
US 11641529B2 · Nishihara et al. · 2023 [cited by applicant]
US 20040130757A1 · Mabuchi · 2004 [cited by applicant]
US 20070222483A1 · Lee · 2007 [cited by applicant]
US 20140139713A1 · Gomi · 2014 [cited by examiner]
US 20160134824A1 · Gomi · 2016 [cited by applicant]
US 20160150175A1 · Hynecek · 2016 [cited by examiner]
US 20170359532A1 · Yuan · 2017 [cited by examiner]
US 20230224601A1 · Nishihara et al. · 2023 [cited by applicant]
JP 2004140149 · 2004 [cited by applicant]
JP 2007074435 · 2007 [cited by applicant]
JP 2012248952 · 2012 [cited by applicant]
International Search Report for International (PCT) Patent Application No. PCT/JP2017/025656, dated Oct. 3, 2017, 1 page. [cited by applicant]
Official Action (with English translation) for Japan Patent Application No. 2018-529771, dated Jul. 13, 2021, 27 pages. [cited by applicant]
Official Action for U.S. Appl. No. 16/318,650, dated Jan. 24, 2020, 10 pages. [cited by applicant]
Notice of Allowance for U.S. Appl. No. 16/318,650, dated May 8, 2020, 7 pages. [cited by applicant]
Official Action for U.S. Appl. No. 16/996,745, dated Oct. 5, 2021, 10 pages. [cited by applicant]
Notice of Allowance for U.S. Appl. No. 16/996,745, dated Apr. 12, 2022, 7 pages. [cited by applicant]
Notice of Allowance for U.S. Appl. No. 17/863,279, dated Dec. 21, 2022, 10 pages. [cited by applicant]
Corrected Notice of Allowance for U.S. Appl. No. 17/863,279, dated Jan. 5, 2023, 2 pages. [cited by applicant]
Notice of Allowance for U.S. Appl. No. 18/124,410, dated Jul. 24, 2023, 11 pages. [cited by applicant]
Corrected Notice of Allowance for U.S. Appl. No. 18/124,410, dated Aug. 4, 2023, 2 pages. [cited by applicant]