Forksheet field effect transistor including t-shaped backbone
A semiconductor device includes a first-type transistor, a second-type transistor, and a t-shaped backbone. The first-type transistor includes a first-type source/drain and the second-type transistor includes a second-type source/drain. The t-shaped backbone includes a wall and a sub-wall. The wall separates the first-type transistor and the second-type source/drain. The sub-wall extends from the wall and into the second-type source/drain.
1 . A method for forming a semiconductor device, the method comprising:
forming a t-shaped backbone in a stack of nanosheets, the t-shaped backbone including a dielectric wall separating the stack of nanosheets into a first-type nanosheet structure and a second-type nanosheet structure, and including a sub-wall extending into a second-type source/drain region of the second-type nanosheet structure;
forming a first source/drain cavity in a first-type source/drain region of the first-type nanosheet structure and a second source/drain cavity in the second-type nanosheet structure, the sub-wall dividing the second source/drain cavity into a first source/drain sub-cavity and a second source/drain sub-cavity;
performing a conformal deposition process that completely fills the first source/drain sub-cavity and the second source/drain sub-cavity with a dielectric material without completely filing the first source/drain cavity with the dielectric material;
removing a first portion of the dielectric material from the first source/drain cavity, and forming a first-type source/drain in the first source/drain cavity while a second portion of the dielectric material prevents formation of the first-type source/drain in the second source/drain cavity; and
removing the second portion of the dielectric material and forming a second-type source/drain in the first source/drain sub-cavity and the second source/drain sub-cavity.
2 . The method of claim 1 , wherein forming the t-shaped backbone comprises:
forming a first trench in the stack of nanosheets to define a first-type transistor region designated to include the first-type nanosheet structure and a second-type transistor region designated to include the second-type nanosheet structure;
forming a second trench extending from the first trench into the second-type source/drain region; and
filling the first trench and the second trench with at least one material that forms the t-shaped backbone.
3 . The method of claim 2 , further comprising:
forming a first gate that wraps around the first-type nanosheet structure to define a first-type transistor; and
forming a second gate that wraps around the second-type nanosheet structure to define a second-type transistor.
4 . The method of claim 3 , wherein:
the first-type nanosheet structure, the first-type source/drain region, and the first-type source/drain corresponds to a p-type field effect transistor (PFET); and
the second-type nanosheet structure, the second-type source/drain region, and the second-type source/drain corresponds to an n-type field effect transistor (NFET).
5 . The method of claim 3 , wherein:
the first-type nanosheet structure, the first-type source/drain region, and the first-type source/drain corresponds to an n-type field effect transistor (NFET); and
the second-type nanosheet structure, the second-type source/drain region, and the second-type source/drain corresponds to a p-type field effect transistor (PFET).
6 . The method of claim 2 , wherein the at least one material comprises the dielectric material.
7 . The method of claim 6 , wherein the dielectric material comprises silicon dioxide (SiO2).
8 . The method of claim 3 , wherein filling the first trench and the second trench with the at least one material comprises:
filling the first trench with the dielectric material; and
filling the second trench with a semiconductor material.
9 . The method of claim 8 , wherein the dielectric material comprises silicon dioxide (SiO2) and the semiconductor material comprises silicon germanium (SiGe) or silicon, depending if pFET or nFET.
10 . A method of forming a forksheet field effect transistor (FET), the method comprising:
forming a stack of nanosheets on a substrate;
forming a t-shaped backbone including a wall and a sub-wall extending from the wall, the wall separating the stack of nanosheets into a first-type nanosheet structure and a second-type nanosheet structure;
patterning the first-type nanosheet structure to form at least two first-type nanosheet fins separated from one another by a first source/drain, and patterning the second-type nanosheet structure to form at least two second-type nanosheet fins separated from one another by a second-type source/drain; and
forming a first gate and a second gate that wrap around the at least two first-type nanosheet fins, respectively, to form a first-type transistor, and forming a third gate and a fourth gate that wrap around the at least two second-type nanosheet fins, respectively, to form a second-type transistor,
wherein the sub-wall extends into the second-type source/drain.
11 . The method of claim 10 , wherein the sub-wall separates a first portion of the second-type source/drain from a second portion of the second-type source/drain.
12 . The method of claim 11 , wherein the wall separates the first-type transistor from the second-type transistor.