Semiconductor device for recessed fin structure having rounded corners
View Patent ↗In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, a plasma process combining etching and deposition processes is used to form a recess having a rounded corner shape in a cross section along the second direction.
1 . A semiconductor device comprising:
an isolation insulating layer disposed over a substrate;
a plurality of fin structures disposed over the substrate and extending in a first direction in plan view;
a merged source/drain epitaxial layer disposed over the plurality of fin structures;
a dielectric layer disposed on the isolation insulating layer and the merged source/drain epitaxial layer;
a first via plug contacting the merged source/drain epitaxial layer; and
a second via plug contacting the merged source/drain epitaxial layer,
wherein:
the first via plug and the second via plug are electrically coupled to different circuit elements from each other,
top portions of the plurality of fin structures are recessed below an upper surface of the isolation insulating layer to form a plurality of recesses, and
a ratio of a first depth D 1 of a recess of the plurality of recesses measured from a topmost portion of the recess to a bottommost surface of the recess to a second depth D 2 of the recess measured from a topmost surface of the isolation insulating layer to the bottommost surface of the recess D 2 /D 1 ranges from 1.9 to 1.14.
2 . The semiconductor device of claim 1 , further comprising:
a gate structure disposed over parts of the plurality of fin structures, and extending in a second direction crossing the first direction; and
a void formed between the merged source/drain epitaxial layer and the upper surface of the isolation insulating layer,
wherein the void has a shape of a trapezoid or a triangle in the first direction in cross sectional view.
3 . The semiconductor device of claim 2 , wherein each interface between the merged source/drain epitaxial layer and each of the plurality of recesses has a rounded corner shape both in a cross section along the first direction and in a cross section along the second direction.
4 . The semiconductor device of claim 3 , wherein the rounded corner shape is one of a U-shape and a bullet head shape in the cross section along the second direction.
5 . The semiconductor device of claim 3 , wherein the rounded corner shape is other than a semi-circular shape in the cross section along the second direction.
6 . The semiconductor device of claim 3 , wherein the interfaces have a U-shape having a straight bottom in a cross section along the first direction.
7 . The semiconductor device of claim 6 , wherein the rounded corner shape is a semi-circular shape in the cross section along the second direction.
8 . The semiconductor device of claim 3 , wherein curved portions of the rounded corner shape do not have a constant curvature.
9 . The semiconductor device of claim 1 , wherein the second depth D 2 ranges from 10 nm to 15 nm.
10 . The semiconductor device of claim 1 , wherein the first depth D 1 ranges from 5 nm to 10 nm.
11 . The semiconductor device of claim 1 , wherein an upper surface of the merged source/drain epitaxial layer has an uneven surface.
12 . The semiconductor device of claim 11 , wherein a peak-to-valley value of the uneven upper surface of the merged source/drain epitaxial layer in the second direction is in a range from 5 nm to 20 nm.
13 . The semiconductor device of claim 1 , wherein two or more gate structures are disposed over the plurality of fin structures.
14 . A semiconductor device comprising:
an isolation insulating layer disposed over a substrate;
a first fin structure and a second fin structure, both disposed over the substrate and extending in a first direction in plan view;
a merged source/drain epitaxial layer disposed over the first and second fin structures;
a dielectric layer disposed on the isolation insulating layer and the merged source/drain epitaxial layer;
a first via plug contacting the merged source/drain epitaxial layer; and
a second via plug contacting the merged source/drain epitaxial layer,
wherein:
the first via plug and the second via plug are electrically coupled to different circuit elements from each other,
top portions of the first and second fin structures are recessed below an upper surface of the isolation insulating layer, and
a void is formed between the merged source/drain epitaxial layer and the upper surface of the isolation insulating layer.
15 . The semiconductor device of claim 14 , further comprising:
a gate structure disposed over parts of the first and second fin structures, and extending in a second direction crossing the first direction.
16 . The semiconductor device of claim 14 , wherein the void has a shape of a trapezoid or a triangle in the first direction in plan view.
17 . The semiconductor device of claim 14 , wherein the interfaces have a U-shape having a straight bottom in a cross section along the first direction.
18 . The semiconductor device of claim 17 , wherein the rounded corner shape is a semi-circular shape in the cross section along the second direction.
19 . A semiconductor device comprising:
an isolation insulating layer disposed over a substrate;
a fin structure disposed over the substrate and extending in a first direction in plan view;
a source/drain epitaxial layer disposed on the fin structure;
a fin mask layer formed over the isolation insulating layer, and over a portion of the source/drain epitaxial layer, comprising a sleeve-like portion having sidewalls that extend away from a top surface of the isolation insulating layer on opposite sides of the fin structure in a cross-sectional view defined by a cross-section plane that is perpendicular to the first direction;
a dielectric layer disposed on the isolation insulating layer and the source/drain epitaxial layer, wherein:
a top portion of the fin structure is recessed below an upper surface of the isolation insulating layer and a source/drain region of the fin structure is embedded in the isolation insulating layer and extends from the substrate toward the upper surface of the isolation insulating layer by about 45 nm to 90 nm,
an interface between the source/drain epitaxial layer and the recessed fin structure has a rounded corner shape both in a cross section along the first direction and in a cross section along a second direction crossing the first direction,
wherein,
a depth of the interface measured from the upper surface of the isolation insulating layer is in a range from 10 nm to 15 nm, and
a void is formed between the source/drain epitaxial layer and the upper surface of the isolation insulating layer.
20 . The semiconductor device of claim 1 , wherein a source/drain region of each fin structure is embedded in the isolation insulating layer and extends from the substrate toward the upper surface of the isolation insulating layer by about 45 nm to 90 nm.