Thermal CVD of titanium silicide methods to form semiconductor structures
Methods of depositing titanium silicide (TiSi) in the formation of semiconductor structures are described. The methods include thermal chemical vapor deposition (CVD) in which a semiconductor substrate in a semiconductor processing chamber is exposed to a titanium-containing precursor, a silicon-containing precursor, and hydrogen (H 2 ) to deposit the titanium silicide (TiSi) layer directly on the semiconductor substrate. Methods of selectively depositing titanium silicide (TiSi) in the formation of semiconductor structures, e.g., an n-type transistor and a p-type transistor, are also described.
1 . A method comprising:
exposing a semiconductor structure including a semiconductor substrate in a semiconductor processing chamber to a first titanium-containing precursor, a first silicon-containing precursor, and a first reactant comprising hydrogen (H 2 ) to deposit a first titanium silicide (TiSi) layer directly on the semiconductor substrate; and
exposing the semiconductor substrate to a second titanium-containing precursor, a second silicon-containing precursor, and a second reactant comprising hydrogen (H 2 ) to deposit a second titanium silicide (TiSi) layer directly on the first titanium silicide (TiSi) layer, wherein each of the first titanium silicide (TiSi) layer and the second titanium silicide (TiSi) layer is independently deposited by thermal CVD, and the first titanium silicide (TiSi) layer is configured as a nucleation layer for further deposition of the second titanium silicide (TiSi) layer thereon.
2 . The method of claim 1 , wherein the semiconductor substrate comprises one or more of doped or undoped crystalline silicon (Si), doped or undoped crystalline silicon germanium (SiGe), doped or undoped amorphous silicon (Si), or doped or undoped amorphous silicon germanium (SiGe).
3 . The method of claim 1 , further comprising pre-cleaning the semiconductor substrate to remove native oxides prior to depositing the first titanium silicide (TiSi) layer.
4 . The method of claim 1 , wherein the first titanium-containing precursor, the first silicon-containing precursor, and the first reactant comprising hydrogen (H 2 ) are continuously flowed in a carrier gas comprising argon (Ar), and the second titanium-containing precursor, the second silicon-containing precursor, and the second reactant comprising hydrogen (H 2 ) are continuously flowed in a carrier gas comprising argon (Ar).
5 . The method of claim 1 , wherein the first titanium-containing precursor is pulsed and purged while the first silicon-containing precursor and the first reactant comprising hydrogen (H 2 ) are continuously flowed in a carrier gas comprising argon (Ar), and the second titanium-containing precursor is pulsed and purged while the second silicon-containing precursor and the second reactant comprising hydrogen (H 2 ) are continuously flowed in a carrier gas comprising argon (Ar).
6 . The method of claim 1 , wherein the first silicon-containing precursor is pulsed and purged while the first titanium-containing precursor and the first reactant comprising hydrogen (H 2 ) are continuously flowed in a carrier gas comprising argon (Ar), and the second silicon-containing precursor is pulsed and purged while the second titanium-containing precursor and the second reactant comprising hydrogen (H 2 ) are continuously flowed in a carrier gas comprising argon (Ar).
7 . The method of claim 1 , wherein one or more of the first titanium-containing precursor and the second titanium-containing precursor comprise titanium tetrachloride (TiCl 4 ).
8 . The method of claim 7 , wherein the titanium tetrachloride (TiCl 4 ) is flowed in a range of from 1 sccm to 20 sccm.
9 . The method of claim 1 , wherein one or more of the first silicon-containing precursor and the second silicon-containing precursor comprise silane (SiH 4 ).
10 . The method of claim 9 , wherein the silane (SiH 4 ) is flowed in a range of from 100 sccm to 3000 sccm.
11 . The method of claim 1 , wherein one or more of the first reactant comprising hydrogen (H 2 ) and the second reactant comprising hydrogen (H 2 ) are flowed in a range of from 500 sccm to 10000 sccm.
12 . The method of claim 1 , wherein the semiconductor processing chamber is maintained at a temperature in a range of from 300° C. to 600° C.
13 . The method of claim 1 , wherein the semiconductor processing chamber is maintained at a pressure in a range of from 50 Torr to 100 Torr.
14 . The method of claim 1 , wherein one or more of the first titanium silicide (TiSi) layer and the second titanium silicide (TiSi) layer have a ratio of titanium:silicon (Ti:Si) in a range of from 1:1 to 2:1.
15 . The method of claim 1 , wherein the second titanium silicide (TiSi) layer has a thickness that is greater than a thickness of the first titanium silicide (TiSi) layer.
16 . A method comprising:
pre-cleaning a semiconductor substrate of a semiconductor structure in a semiconductor processing chamber to remove native oxides and form a cleaned semiconductor substrate; and
exposing the cleaned semiconductor substrate to titanium tetrachloride (TiCl 4 ), silane (SiH 4 ), and hydrogen (H 2 ) by a thermal chemical vapor deposition (CVD) process to deposit a titanium silicide (TiSi) layer directly on the cleaned semiconductor substrate, wherein one or more of the titanium tetrachloride (TiCl 4 ) and the silane (SiH 4 ) are pulsed and purged while the hydrogen (H 2 ) and the other of the titanium tetrachloride (TiCl 4 ) and the silane (SiH 4 ) are continuously flowed in a carrier gas comprising argon (Ar), wherein the semiconductor structure comprises an n-type transistor and a p-type transistor, a first opening over the n-type transistor, and a second opening over the p-type transistor, and the titanium silicide (TiSi) layer selectively forms on a source/drain material of the n-type transistor and a source/drain material of the p-type transistor.
17 . The method of claim 16 , further comprising forming a capping layer on the titanium silicide (TiSi) layer.
18 . The method of claim 17 , wherein the capping layer is selected from one or more of titanium nitride (TIN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), tungsten (W), molybdenum (Mo), and ruthenium (Ru).
19 . The method of claim 18 , further comprising depositing a gap fill material to fill one or more of the first opening or the second opening.
20 . The method of claim 18 , wherein the capping layer includes a first capping layer and a second capping layer, the first capping layer comprising one or more of selectively deposited tungsten (W) or selectively deposited molybdenum (Mo), and the second capping layer comprising one or more of PVD tungsten (W) or PVD molybdenum (Mo).