IP Library › Granted Patent US 12,205,906
Granted Patent B2
US 12,205,906 · App. 18/537,638 · Granted Jan 21, 2025

Electronic package and fabrication method thereof

Inventors: Yu-Lung Huang (Taichung, TW); Chee-Key Chung (Taichung, TW); Yuan-Hung Hsu (Taichung, TW); Chi-Jen Chen (Taichung, TW)
Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
H01L23/562H01L21/76804H01L23/5384H01L23/5386
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Quick Facts
Patent No.
US 12,205,906
App. No.
18/537,638
Granted
Jan 21, 2025
Kind
B2
Abstract

An electronic package is provided and includes a plurality of electronic elements, a spacing structure connecting each of the plurality of electronic elements, and a plurality of conductive elements electrically connected to the plurality of electronic elements and serving as external contacts. The spacing structure has a recess to enhance the flexibility of the electronic elements after the electronic elements are connected to one another, thereby preventing the problem of warpage. A method for fabricating the electronic package is also provided.

Claims (15)

1. A method for fabricating an electronic package, comprising:

providing a plurality of electronic elements;

forming a spacing structure between any adjacent two of the plurality of electronic elements for connecting the adjacent two of the electronic elements, wherein a filling material and an encapsulant constitute the spacing structure, wherein the filling material is formed between the adjacent two of the plurality of electronic elements, the filling material is in contact with opposing side surfaces of the adjacent two of the plurality of electronic elements, and a first recess is formed within the filling material, and wherein the encapsulant is formed in the first recess, and a second recess is formed within the encapsulant;

and

providing a plurality of conductive elements electrically connected to the plurality of electronic elements to serve as external contacts.

2. The method of claim 1 , further comprising providing a carrier structure having two opposite sides, wherein one of the two opposite sides of the carrier structure carries and is electrically connected to the plurality of electronic elements, and the plurality of conductive elements are disposed on the other one of the two opposite sides of the carrier structure.

3. The method of claim 2 , wherein the carrier structure is in a form of a single carrier board or in a form of multiple carrier boards.

4. The method of claim 2 , wherein the filling material is formed between the plurality of electronic elements and the carrier structure.

5. The method of claim 1 , further comprising encapsulating the plurality of electronic elements by the encapsulant.

6. The method of claim 1 , wherein each of the electronic elements has an active surface, an inactive surface opposite to the active surface, and the side surface adjacent to and connecting the active surface and the inactive surface, and the spacing structure connects the side surfaces of the plurality of electronic elements.

7. The method of claim 1 , wherein the second recess has an inclined surface formed on a top wall thereof.

8. The method of claim 7 , wherein the inclined surface extends to the adjacent two of the electronic elements.

9. The method of claim 1 , further comprising bonding a heat dissipation element onto the plurality of electronic elements, wherein the heat dissipation element covers the second recess.

10. The method of claim 9 , wherein the heat dissipation element is bonded onto the plurality of electronic elements through a bonding layer.

11. The method of claim 10 , wherein the bonding layer is partially filled in the second recess.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2023
From: HUANG, YU-LUNG; CHUNG, CHEE-KEY; HSU, YUAN-HUNG; CHEN, CHI-JEN
To: SILICONW ARE PRECISION INDUSTRIES CO., LTD.
Reel/Frame 065859/0679 →
Priority Claims (1)
TW 108133228 · Sep 16, 2019 · national
Continuity (2)
Division 16867937 · May 6, 2020
Related Publication 20240162169A1 · May 16, 2024
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