Transient stabilized SOI FETs
Integrated circuits (ICs) that avoid or mitigate creation of changes in accumulated charge in a silicon-on-insulator (SOI) substrate, particularly an SOI substrate having a trap rich layer. In one embodiment, a FET is configured such that, in a standby mode, the FET is turned OFF while maintaining essentially the same V DS as during an active mode. In another embodiment, a FET is configured such that, in a standby mode, current flow through the FET is interrupted while maintaining essentially the same V GS as during the active mode. In another embodiment, a FET is configured such that, in a standby mode, the FET is switched into a very low current state (a “trickle current” state) that keeps both V GS and V DS close to their respective active mode operational voltages. Optionally, S-contacts may be formed in an IC substrate to create protected areas that encompass FETs that are sensitive to accumulated charge effects.
1. A method for eliminating or reducing changes in accumulated charge in a circuit fabricated on a silicon-on-insulator (SOI) substrate including a trap rich layer susceptible to accumulated charge in or near such trap rich layer, the method including:
(a) providing a P-type field effect transistor (PFET) having a drain, a source, a gate, a V GS characteristic, and a signal path through the PFET between the drain and the source;
(b) coupling a first terminal of a controlled through-path switch to the drain of the PFET and a second terminal of the controlled through-path switch to a load, and configuring the controlled through-path switch to selectively couple the signal path of the PFET to the load when the controlled through-path switch is in a closed state or interrupt current flow through the signal path of the PFET when the controlled through-path switch is in an open state;
(c) coupling the source of the PFET to a supply voltage V DD ;
(d) in an active mode, setting the controlled through-path switch to couple the signal path of the PFET to the load; and
(e) in a standby mode, setting the controlled through-path switch to interrupt current flow through the signal path of the PFET, thereby maintaining essentially the same V GS characteristic as during the active mode, and thereby eliminating or reducing changes in accumulated charge.
2. The method of claim 1 , further including providing at least one substrate contact near the PFET.
3. The method of claim 1 , further including providing at least a partial ring of substrate contacts around the PFET.
4. A method for eliminating or reducing changes in accumulated charge in an integrated circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, including:
(a) providing at least one field effect transistor (FET) having a drain, a source, a gate, a V DS characteristic, a V GS characteristic, and a signal path through the FET between the drain and the source;
(b) coupling a switch to the signal path of the FET, the switch configured to selectively couple the signal path to a first current source or to a second current source, the second current source providing a trickle current lower than the first current source;
(c) in an active mode, setting the switch to couple the signal path of the FET to the first current source; and
(d) in a standby mode, setting the switch to couple the signal path of the FET to the second current source, such that both the V GS characteristic and the V DS characteristic of the FET are close to respective active mode operational voltages for the V GS characteristic and the V DS characteristic, thereby reducing changes in accumulated charge.
5. The method of claim 4 , wherein the SOI substrate includes a trap rich layer susceptible to accumulated charge in or near such trap rich layer.
6. The method of claim 4 , further including providing at least one substrate contact near at least one FET.
7. The method of claim 4 , further including providing at least a partial ring of substrate contacts around at least one FET.
8. The method of claim 1 , further including coupling a bias voltage to a gate of the PFET.
9. The method of claim 1 , wherein the controlled through-path is implemented as a FET.
10. The method of claim 1 , wherein the controlled through-path functions as a single-pole, single throw switch.
11. The method of claim 4 , wherein the at least one FET is a P-type FET.
12. The method of claim 4 , wherein the at least one FET is a N-type FET.
13. The method of claim 4 , wherein the switch is a FET.
14. The method of claim 4 , further including coupling a first bias voltage to a gate of the at least one FET.
15. The method of claim 4 , further including coupling a first bias voltage to a gate of the at least one FET in the active mode, and coupling a second bias voltage to a gate of the at least one FET in the standby mode.
16. The method of claim 4 , wherein the first current source is a first resistor coupled to a first voltage potential, and the second current source is a second resistor coupled to a second voltage potential.
17. The method of claim 16 , wherein the resistance of the second resistor is substantially greater than the resistance of the first resistor.
18. The method of claim 16 , wherein the ratio of resistances of the second resistor to the first resistor ranges from approximately 100:1 to approximately 1000:1.
19. A method for eliminating or reducing changes in accumulated charge in a circuit fabricated on a silicon-on-insulator (SOI) substrate including a trap rich layer susceptible to accumulated charge in or near such trap rich layer, the method including:
(a) providing a P-type field effect transistor (PFET) having a drain, a source, a gate, a V GS characteristic, and a signal path through the PFET between the drain and the source;
(b) coupling a first terminal of a controlled through-path switch to the drain of the PFET and a second terminal of the controlled through-path switch to a load, and configuring the controlled through-path switch to selectively couple the signal path of the PFET to the load when the controlled through-path switch is in a closed state or interrupt current flow through the signal path of the PFET when the controlled through-path switch is in an open state, wherein the controlled through-path is implemented as a FET;
(c) coupling the source of the PFET to a supply voltage VDD;
(d) coupling a bias voltage to a gate of the PFET;
(e) in an active mode, setting the controlled through-path switch to couple the signal path of the PFET to the load; and
(f) in a standby mode, setting the controlled through-path switch to interrupt current flow through the signal path of the PFET, thereby maintaining essentially the same V GS characteristic as during the active mode, and thereby eliminating or reducing changes in accumulated charge.
20. The method of claim 19 , further including providing at least a partial ring of substrate contacts around the PFET.