IP Library Granted Patent US 9,236,374
Granted Patent B2
US 9,236,374 · App. 14/146,421 · Granted Jan 12, 2016

Fin contacted electrostatic discharge (ESD) devices with improved heat distribution

Inventors: John B. Campi, Jr. (Westford, VT); Robert J. Gauthier, Jr. (Hinesburg, VT); Rahul Mishra (Essex Junction, VT); Souvick Mitra (Essex Junction, VT); Mujahid Muhammad (Essex Junction, VT)
Assignee: GLOBALFOUNDRIES INC.
H01L27/0262H01L23/3677H01L27/0255H01L29/66545H01L2924/0002
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Quick Facts
Patent No.
US 9,236,374
App. No.
14/146,421
Granted
Jan 12, 2016
Kind
B2
Abstract

Fin contacted electrostatic discharge (ESD) devices with improved heat distribution and methods of manufacture are disclosed. The method includes forming a plurality of fins on a substrate which is aligned with at least one well region in the substrate. The method further includes forming at least one electrostatic discharge (ESD) device spanning two or more of the plurality of fins. The forming of the ESD device includes forming an epitaxial material spanning the two or more of the plurality of fins and forming one or more contacts on the epitaxial material.

Claims (35)

1. A method comprising:

forming a plurality of fins on a substrate comprising at least a pair of P+ fins and at least a pair of N+ fins which are aligned with at least one well region in the substrate; and

forming at least one electrostatic discharge (ESD) device spanning two or more of the plurality of fins, wherein the forming of the ESD device comprises:

forming an epitaxial material spanning the two or more of the plurality of fins; and

forming one or more contacts on the epitaxial material.

2. The method of claim 1 , further comprising forming a device bounded by shallow trench isolation (STI) structures in the substrate, in FinFET technology.

3. The method of claim 2 , wherein the STI bounded device is formed with a buried channel which increases an Si volume in FinFET technology.

4. The method of claim 3 , wherein the STI bounded device with the buried channel provides improved heat dissipation in FinFET technology.

5. The method of claim 1 , wherein the at least one well region is two well regions comprising forming an N-well region abutting against a P-well region.

6. The method of claim 5 , wherein:

the at least a pair of P+ fins and the at least a pair of N+ fins are formed in the N-well region and the P-well region; and

the at least one ESD device spans between the at least pair of P+ fins in the N-well region and the P-well region and the at least pair of the N+ fins in the N-well region and the P-well region.

7. The method of claim 5 , further comprising forming a gate structure adjacent to the at least one ESD device, the gate structure spanning the plurality of fins.

8. The method of claim 7 , further comprising forming shallow trench isolation structures in the substrate separating each of the plurality of fins.

9. The method of claim 1 , wherein the forming of the epitaxial material is a growth process which grows the epitaxial material into direct contact with the substrate.

10. The method of claim 1 , wherein the forming of the epitaxial material is a growth process which grows the epitaxial material above the substrate.

11. The method of claim 1 , wherein the at least one well region is an N-well region and the at least a pair of P+ fins and the at least a pair of N+ fins are formed on the N-well region.

12. The method of claim 11 , wherein the at least one ESD device spans between the at least pair of P+ fins on the N-well region and at least two separate pairs of the N+ fins on the N-well region, and further comprising forming a gate structure adjacent to the at least one ESD device, the gate structure spanning the plurality of fins and forming a heat sink to dissipate heat generated from the at least one ESD device to the substrate, wherein the forming the gate structure includes a replacement gate process.

13. The method of claim 12 , further comprising forming shallow trench isolation structures within the N-well region and between each of the plurality of fins.

14. A method comprising:

forming at least one well region in a substrate;

forming a plurality of fins over the at least one well region comprising at least a pair of P+ fins and at least a pair of N+ fins;

forming a plurality of ESD devices spanning sets of the plurality of fins, the forming of the plurality of ESD devices comprises:

growing epitaxial material on the sets of the plurality of fins; and

forming contacts on the epitaxial material;

forming metal gate structures spanning the plurality of fins and separating each of the plurality of ESD devices along lengths of the sets of the plurality of fins; and

forming shallow trench isolation structures within the at least one well region and between each of the plurality of fins.

15. The method of claim 14 , wherein the at least one well region is two well regions, including an N-well region abutting against a P-well region.

16. The method of claim 15 , wherein:

the at least a pair of P+ fins and the at least a pair of N+ fins are formed in the N-well region and the P-well region; and

the plurality of ESD devices span between the at least pair of P+ fins in the N-well region and the P-well region and the at least pair of N+ fins in the N-well region and the P-well region.

17. The method of claim 14 , wherein the forming of the epitaxial material is a growth process.

18. The method of claim 14 , wherein:

the at least one well region is an N-well region and the at least pair of P+ fins and the at least pair of N+ fins are formed on the N-well region; and each of the plurality of ESD devices span between the at least pair of P+ fins on the N-well region and at least two separate pairs of the N+ fins on the N-well region.

19. The method of claim 18 , wherein the metal gate structures are adjacent to each of the plurality of ESD devices and act as heat sinks to dissipate heat generated from the ESD devices into the substrate.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 2, 2014
From: CAMPI, JOHN B., JR.; GAUTHIER, ROBERT J., JR.; MISHRA, RAHUL; MITRA, SOUVICK; MUHAMMAD, MUJAHID
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 031881/0575 →
Continuity (1)
Related Publication 20150187753A1 · Jul 2, 2015