RF switch stack with charge redistribution
Methods and devices to address body leakage current generation and bias voltage distribution associated with body leakage current in an OFF state of a FET switch stack are disclosed. The devices include charge redistribution arrangements and bridge networks to perform coupling/decoupling to/from the FET switch stack. Detailed structures of such bridge networks are also described.
1. A field effect transistor (FET) switch stack circuit comprising:
i) a plurality of series-connected FET transistors arranged in a stacked configuration;
ii) a drain/source charge redistribution resistive ladder having a set of drain/source tapping points corresponding to drains or sources of the series-connected FET transistors;
iii) a body charge redistribution resistive ladder having a set of body tapping points corresponding to bodies of the series-connected FET transistors;
iv) a body resistive ladder comprising body resistors, each coupling body-terminals of a corresponding pair of adjacent FET transistors of the plurality of series-connected FET transistors,
wherein the set of drain/source tapping points and the set of body tapping points are configured to be selectively coupled/decoupled with/from each other.
2. The FET switch of claim 1 , further comprising a drain-body bridge network performing the selective coupling/decoupling.
3. The FET switch stack circuit of claim 2 , wherein the drain-body bridge network comprises at least one drain-body bridge circuit.
4. The FET switch stack circuit of claim 3 , wherein each drain-body bridge circuit is a combination of a drain/source bridge circuit and a body bridge circuit, the drain/source bridge circuit connected between the drain/source charge redistribution resistive ladder and the body bridge circuit, the body bridge circuit connected between the drain/source bridge circuit and the body charge redistribution resistive ladder.
5. The FET switch stack circuit of claim 4 , wherein the series-connected FET transistors are coupled to a radio frequency (RF) terminal.
6. The FET switch circuit of claim 5 , wherein:
the drain/source charge redistribution ladder is coupled to the RF terminal; and
the body charge redistribution ladder is coupled at one end to the RF terminal.
7. The FET switch stack circuit of claim 6 , wherein when the FET switch stack is in an OFF state, the FET switch stack is configured to be coupled to an RF signal at the RF terminal, and to couple RF voltages at source/drain tapping points of the set of one or more drain/source tapping points and at body tapping points of the set of one or more body tapping points.
8. The FET switch stack circuit of claim 6 , wherein when the FET switch stack is in an OFF state, the drain-body bridge circuits are configured to couple the body tapping points to the drain/source tapping points during a first portion of a period of the RF signal.
9. The FET switch stack circuit of claim 8 , wherein, when the FET switch stack is in the OFF state, the drain-body bridge circuits are configured to decouple the body tapping points from the drain/source tapping points during a second portion of the period of the RF signal separate from the first portion.
10. The FET switch stack circuit of claim 4 , wherein the drain/source bridge circuit comprises a diode element having
a cathode node connected to a drain terminal of a corresponding FET transistor of the FET switch stack, and
an anode node coupled to a corresponding drain/source tapping point of the drain/source charge redistribution resistive ladder.
11. The FET switch stack of claim 10 , wherein the diode element comprises one or more diode-connected transistors arranges in a series configuration.
12. The FET switch stack circuit of claim 4 , wherein the body bridge circuit comprises a diode element having
a cathode node connected to a body terminal of a corresponding FET transistor of the FET switch stack, and
an anode node coupled to a corresponding body tapping point of the body charge redistribution resistive ladder.
13. The FET switch stack of claim 12 , wherein the diode element comprises one or more diode-connected transistors arranges in a series configuration.
14. A field effect transistor (FET) switch stack circuit comprising:
i) a plurality of series-connected FET transistors arranged in a stacked configuration,
ii) a drain/source charge redistribution resistive ladder having a set of drain/source tapping points corresponding to drains or sources of the series-connected FET transistors; and
iii) a body charge redistribution resistive ladder having a set of body tapping points corresponding to bodies of the series-connected FET transistors,
wherein the set of drain/source tapping points and the set of body tapping points are configured to be selectively coupled/decoupled with/from each other.