Multi-gate devices and fabricating the same with etch rate modulation
The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members vertically stacked above a substrate, a gate structure engaging the channel members, a gate sidewall spacer disposed on a sidewall of the gate structure, an epitaxial feature abutting end portions of the channel members, and inner spacers interposing the gate structure and the epitaxial feature. The end portion of at least one of the channel members includes a first dopant. A concentration of the first dopant in the end portion of the at least one of the channel members is higher than in a center portion of the at least one of the channel members. The concentration of the first dopant in the end portion of the at least one of the channel members is higher than in an outer portion of the epitaxial feature.
1. A semiconductor device, comprising:
channel members vertically stacked above a substrate;
a gate structure engaging the channel members;
a gate sidewall spacer disposed on a sidewall of the gate structure;
an epitaxial feature abutting end portions of the channel members; and
inner spacers interposing the gate structure and the epitaxial feature,
wherein:
the end portion of at least one of the channel members includes a first dopant,
a concentration of the first dopant in the end portion of the at least one of the channel members is higher than in a center portion of the at least one of the channel members, and
the concentration of the first dopant in the end portion of the at least one of the channel members is higher than in an outer portion of the epitaxial feature.
2. The semiconductor device of claim 1 , wherein the end portion of the at least one of the channel members is flush with a sidewall of the gate sidewall spacer.
3. The semiconductor device of claim 1 , wherein the at least one of the channel members has a length smaller than adjacent ones of the channel members.
4. The semiconductor device of claim 3 , wherein the end portions of the adjacent ones of the channel members extrude away from a sidewall of the gate sidewall spacer towards the epitaxial feature.
5. The semiconductor device of claim 1 , wherein the center portion of the at least one of the channel members is substantially free of the first dopant.
6. The semiconductor device of claim 1 , wherein the inner spacers are substantially free of the first dopant.
7. The semiconductor device of claim 1 , wherein the outer portion of the epitaxial feature is substantially free of the first dopant.
8. The semiconductor device of claim 1 , wherein the concentration of the first dopant in the end portion of the at least one of the channel members is lower than in an inner portion of the epitaxial feature.
9. The semiconductor device of claim 1 , wherein the concentration of the first dopant in the end portion of the at least one of the channel members is higher than in an inner portion of the epitaxial feature.
10. The semiconductor device of claim 1 , wherein the first dopant is selected from the group consisting of As, B, and P.
11. A semiconductor device, comprising:
first and second channel members vertically stacked above a substrate;
a gate structure wrapping around each of the first and second channel members;
a gate sidewall spacer disposed on a sidewall of the gate structure; and
an epitaxial feature abutting a first end portion of the first channel member and a second end portion of the second channel member,
wherein the first end portion of the first channel member includes a dopant, and a concentration of the dopant in the first end portion of the first channel member is higher than in the second end portion of the second channel member.
12. The semiconductor device of claim 11 , wherein the second end portion of the second channel member is substantially free of the dopant.
13. The semiconductor device of claim 11 , wherein the first channel member is shorter than the second channel member.
14. The semiconductor device of claim 11 , wherein the first end portion of the first channel member is flush with a sidewall of the gate sidewall spacer, and the second end portion of the second channel member extrudes away from the sidewall of the gate sidewall spacer towards the epitaxial feature.
15. The semiconductor device of claim 11 , wherein the first channel member is above the second channel member.
16. The semiconductor device of claim 11 , wherein the second channel member is above the first channel member.
17. A semiconductor device, comprising:
a channel member disposed over a substrate;
a gate structure wrapping around the channel member;
a gate sidewall spacer disposed on a sidewall of the gate structure; and
an epitaxial feature abutting the channel member,
wherein:
an end portion of the channel member includes a dopant of a first concentration,
an outer portion of the epitaxial feature includes the dopant of a second concentration,
an inner portion of the epitaxial feature includes the dopant of a third concentration,
the first concentration is higher than the second concentration, and
the second concentration is lower than the third concentration.
18. The semiconductor device of claim 17 , wherein the first concentration is lower than the third concentration.
19. The semiconductor device of claim 17 , wherein a top portion of the substrate directly under the epitaxial feature is doped with the dopant.
20. The semiconductor device of claim 17 , wherein a top portion of the substrate directly under the epitaxial feature is substantially free of the dopant.