IP Library › Granted Patent US 12,481,438
Granted Patent B2
US 12,481,438 · App. 18/624,395 · Granted Nov 25, 2025

Data storage device and method for hybrid space balancing based on host read affinity and heuristics

Inventors: Dinesh Kumar Agarwal (Bangalore, IN); Sunny Sharan (Bangalore, IN)
Assignee: Sandisk Technologies, Inc.
G06F3/0631G06F3/0604G06F3/0679
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Quick Facts
Patent No.
US 12,481,438
App. No.
18/624,395
Granted
Nov 25, 2025
Kind
B2
Abstract

A data storage device and method for hybrid space balancing based on host read affinity and heuristics are provided. In one embodiment, a data storage device is provided comprising a memory and one or more processors. The one or more processors, individually or in combination, are configured to: receive information from a host regarding an incoming write workload of a burst operation; and dynamically adjust an amount of the memory configured as single-level cell (SLC) memory versus multi-level cell (MLC) memory based on the information to accommodate the burst operation. Other embodiments are disclosed.

Claims (30)

1 . A data storage device comprising:

a memory; and

one or more processors, individually or in combination, configured to:

receive information from a host regarding an incoming write workload of a burst operation, wherein the information comprises a number of read operations and a number of write operations in a window of time, and wherein a size of the window is dynamically adjustable; and

dynamically adjust an amount of the memory configured as single-level cell (SLC) memory versus multi-level cell (MLC) memory based on the information to accommodate the burst operation.

2 . The data storage device of claim 1 , wherein the window comprises a sliding window.

3 . The data storage device of claim 1 , wherein the information comprises an indication of an affinity toward reads versus writes.

4 . The data storage device of claim 3 , wherein the one or more processors, individually or in combination, are further configured move data from the SLC memory to the MLC memory in response to an indication of an affinity towards writes.

5 . The data storage device of claim 3 , wherein the one or more processors, individually or in combination, are further configured move data from the MLC memory to the SLC memory in response to an indication of an affinity towards reads.

6 . The data storage device of claim 1 , wherein the information is received from the host after the data storage device confirms, with the host, that the data storage device supports dynamic window sizing and hybrid adjustment.

7 . The data storage device of claim 1 , wherein an amount of hybrid space in the memory is a function of an affinity towards reads verses writes, an amount of SLC reads, and an amount of SLC writes.

8 . The data storage device of claim 1 , wherein the MLC memory comprises triple-level cell (TLC) memory.

9 . The data storage device of claim 1 , wherein the MLC memory comprises quad-level cell (QLC) memory.

10 . The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.

11 . A method comprising:

performing in a data storage device comprising a memory:

determining whether a host is exhibiting, over a window of time, an affinity toward writes or an affinity toward reads;

in response to determining that the host is exhibiting an affinity toward writes, moving data from a single-level cell (SLC) block of the memory to a multi-level cell (MLC) block of the memory; and

in response to determining that the host is exhibiting an affinity toward reads, moving data from the MLC block of the memory to the SLC block of the memory:

wherein an amount of hybrid space in the memory is a function of the affinity towards reads verses writes, an amount of SLC reads, and an amount of SLC writes.

12 . The method of claim 11 , further comprising dynamically adjusting a size of the window.

13 . The method of claim 11 , wherein the window comprises a sliding window.

14 . The method of claim 11 , wherein the MLC block of the memory comprises triple-level cell (TLC) memory.

15 . The method of claim 11 , wherein the MLC block of the memory comprises quad-level cell (QLC) memory.

16 . The method of claim 11 , wherein the memory comprises a three-dimensional memory.

17 . A data storage device comprising:

a memory; and

means for:

receiving information from a host regarding an incoming write workload of a burst operation, wherein the information is received from the host after the data storage device confirms, with the host that the data storage device supports dynamic window sizing and hybrid adjustment; and

dynamically adjusting an amount of the memory configured as single-level cell (SLC) memory versus multi-level cell (MLC) memory based on the information to accommodate the burst operation.

Assignments (4)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2024
From: AGARWAL, DINESH KUMAR; SHARAN, SUNNY
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 066983/0135 →
Continuity (1)
Related Publication 20250306784A1 · Oct 2, 2025
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