Gain cell memory device using enhanced sensing scheme and methods for operating the same
A gain cell memory includes a write transistor located on a substrate; a read transistor located on the substrate; a capacitor having a first electrode, a node dielectric, and a second electrode, wherein the first electrode is electrically connected to a first source/drain region of the write transistor and to a gate electrode of the read transistor; and a peripheral circuit configured to electrically bias a source region of the read transistor at a normal source bias voltage while the gain cell memory device is not under a read operation, and at a current-boost source bias voltage that increases an on-current of the read transistor while the gain cell memory device is under the read operation.
1 . A gain cell memory device comprising:
a write transistor located on a substrate;
a read transistor located on the substrate;
a capacitor having a first electrode, a node dielectric, and a second electrode, wherein the first electrode comprises a signal node which is electrically connected to a first source/drain region of the write transistor and to a gate electrode of the read transistor, wherein the write transistor and the read transistor are front-end-of-line field-effect transistors formed directly on semiconductor material portions of the substrate, and the capacitor is a metal-insulator-metal capacitor embedded within dielectric material layers that overlie the write transistor and the read transistor and vertically spaced from the write transistor and the read transistor;
a read bit line configured to electrically bias a drain region of the read transistor;
a source bias line that is connected to a source region of the read transistor; and
a peripheral circuit configured to electrically bias the source bias line at a normal source bias voltage while the gain cell memory device is not under a read operation, and at a current-boost source bias pulse while the gain cell memory device is under the read operation, wherein:
the current-boost source bias pulse has a pulse voltage that equals a sum of (1+α) times the normal source bias voltage plus −α times a pre-charge bias voltage applied to a read bit line, wherein a has α value in a range from 0.01 to 0.30;
a rising edge of the current-boost source bias pulse is synchronous with a rising edge of a read word line pulse applied to a gate of the read transistor or an additional read transistor connected in series with the read transistor; and
a falling edge of the current-boost source bias pulse is synchronous with a falling edge of the read word line pulse.
2 . The gain cell memory device of claim 1 , further the read bit line is configured to electrically bias a drain region of the read transistor during an initial step of the read operation.
3 . The gain cell memory device of claim 2 , further comprising an additional read transistor that is connected to the drain region of the read transistor in a series connection, wherein a drain region of the additional read transistor is electrically shorted to the read bit line.
4 . The gain cell memory device of claim 3 , wherein the peripheral circuit is configured to apply a read gate pulse to a gate electrode of the additional read transistor for a first time duration during the read operation.
5 . The gain cell memory device of claim 4 , wherein:
the first time duration and the pulsed current-boost source bias voltage are selected such that a voltage at the read bit line at a time point of termination of the first time duration is between a first voltage and a second voltage under a condition in which the gate electrode of the read transistor is at a voltage that equals a sum of 0.5 times the pre-charge bias voltage and 0.5 times the normal source bias voltage;
the first voltage equals a sum of 0.4 times the pre-charge bias voltage and 0.6 times the normal source bias voltage; and
the second voltage equals a sum of 0.6 times the pre-charge bias voltage and 0.4 times the normal source bias voltage.
6 . The gain cell memory device of claim 2 , wherein the read bit line is electrically shorted to the drain region of the read transistor.
7 . The gain cell memory device of claim 6 , wherein the peripheral circuit is configured to:
maintain the read bit line at a high impedance state while the gain cell memory device is not under a read operation;
apply a pre-charge bias voltage to the read bit line during a pre-charge step of the read operation; and
measure a voltage at the read bit line after a first time duration after the pre-charge step.
8 . The gain cell memory device of claim 1 , wherein:
the pulsed current-boost source bias voltage is applied as a pulse having a duration equal to a duration of a read gate pulse applied to an additional read transistor connected in series with the read transistor; and
the pulse is generated by the peripheral circuit in response to a read command.
9 . The gain cell memory device of claim 1 , wherein:
the gain cell memory device is a three-transistor one-capacitor (3T1C) gain cell memory device comprising a write transistor, a first read transistor, and a second read transistor;
the capacitor is located within dielectric material layers that overlie the write transistor, the first read transistor, and the second read transistor;
the pulsed current-boost source bias voltage is applied as a pulse having a same time duration as a read gate pulse applied to the first read transistor; and
the pulsed current-boost source bias voltage increases an on-current of the second read transistor during a read operation relative to an operation in which a normal source-bias voltage is applied to the source bias line.
10 . The gain cell memory device of claim 1 , wherein α has a value in a range from 0.03 to 0.15 in the relation for the current-boost source-bias pulse voltage.
11 . The gain cell memory device of claim 1 , wherein applying the current-boost source-bias voltage increases a read bit-line voltage differential relative to a read operation using the normal source-bias voltage.
12 . A gain cell memory device comprising:
a write transistor located on a substrate;
a read transistor located on the substrate;
a capacitor having a first electrode which comprises a signal node that is electrically connected to a first source/drain region of the write transistor and to a gate electrode of the read transistor, a node dielectric, and a second electrode, wherein the write transistor and the read transistor are front-end-of-line field-effect transistors formed directly on semiconductor material portions of the substrate, and the capacitor is a metal-insulator-metal capacitor embedded within dielectric material layers that overlie the write transistor and the read transistor and vertically spaced from the write transistor and the read transistor;
metal interconnect structures located within the dielectric material layers and providing electrical connection to the first electrode, a second source/drain region of the write transistor, and a source region of the read transistor;
a read bit line configured to electrically bias a drain region of the read transistor;
a source bias line electrically connected to the source region of the read transistor; and
a peripheral circuit configured to electrically bias the source bias line at a normal source bias voltage while the gain cell memory device is not under a read operation, and at a current-boost source bias pulse that increases an on-current of the read transistor while the gain cell memory device is under the read operation, wherein:
the current-boost source bias pulse has a pulse voltage that equals a sum of (1+α) times the normal source bias voltage plus −α times a pre-charge bias voltage applied to a read bit line, wherein a has α value in a range from 0.01 to 0.30;
a rising edge of the current-boost source bias pulse is synchronous with a rising edge of a read word line pulse applied to a gate of the read transistor or an additional read transistor connected in series with the read transistor; and
a falling edge of the current-boost source bias pulse is synchronous with a falling edge of the read word line pulse.
13 . The gain cell memory device of claim 12 , wherein:
the peripheral circuit comprises a sense amplifier that is electrically connected to the read bit line; and
the peripheral circuit comprises a data latch that is configured to store an output of the sense amplifier at a time point at which the read operation terminates.
14 . A method of operating a device, the method comprising:
providing a gain cell memory device which comprises a write transistor located on a substrate, a read transistor located on the substrate, a capacitor having a first electrode which comprises a signal node that is electrically connected to a first source/drain region of the write transistor and to a gate electrode of the read transistor, a node dielectric, and a second electrode, a read bit line that is configured to electrically bias a drain region of the read transistor, and a source bias line that is connected to a source region of the read transistor, wherein the write transistor and the read transistor are front-end-of-line field-effect transistors formed directly on semiconductor material portions of the substrate, and the capacitor is a metal-insulator-metal capacitor embedded within dielectric material layers that overlie the write transistor and the read transistor and vertically spaced from the write transistor and the read transistor;
performing a write operation that encodes a data bit in the signal node by applying a write read-bit-line bias voltage to a second source/drain region of the write transistor and by turning on the write transistor while the source bias line is electrically biased at a first source bias voltage; and
performing a read operation by pre-charging the read bit line at a pre-charge bias voltage, by applying to the source bias line a current-boost source bias pulse, and by sensing a voltage at a drain region of the read transistor, wherein:
the current-boost source bias pulse has a pulse voltage that equals a sum of (1+α) times the normal source bias voltage plus −α times a pre-charge bias voltage applied to a read bit line, wherein α has a value in a range from 0.01 to 0.30;
a rising edge of the current-boost source bias pulse is synchronous with a rising edge of a read word line pulse applied to a gate of the read transistor or an additional read transistor connected in series with the read transistor; and
a falling edge of the current-boost source bias pulse is synchronous with a falling edge of the read word line pulse.
15 . The method of claim 14 , wherein a magnitude of a difference between the pre-charge bias voltage and the second source bias voltage is greater than a magnitude of a difference between the pre-charge bias voltage and the first source bias voltage.
16 . The method of claim 14 , wherein:
a first one of the pre-charge bias voltage and the first source bias voltage is a circuit power supply voltage; and
a second one of the pre-charge bias voltage and the first source bias voltage is an electrical ground voltage.
17 . The method of claim 14 , wherein:
the gain cell memory device comprises an additional read transistor configured to switch an electrical connection between the read bit line and the drain region of the read transistor;
the second source bias voltage is applied to the first source bias line by applying a current-boost source bias pulse;
the additional read transistor is turned on by applying a gate voltage pulse to a gate electrode of the additional read transistor; and
the current-boost source bias pulse has a same time duration as the gate voltage pulse.
18 . The method of claim 14 , wherein:
the gain cell memory device comprises a sense amplifier that is electrically connected to the read bit line and a data latch that is electrically coupled to an output of the sense amplifier; and
the method further comprises capturing the output of the sense amplifier at a time point at which the read operation terminates using the data latch.
19 . The method of claim 14 , wherein α has a value in a range from 0.03 to 0.15.
20 . The method of claim 14 , wherein applying the current-boost source-bias voltage increases a read bit-line voltage differential relative to a read operation using the normal source-bias voltage.