IP Library Granted Patent US 12,412,819
Granted Patent B2
US 12,412,819 · App. 18/643,424 · Granted Sep 9, 2025

Electronic package and manufacturing method thereof

Inventors: Yi-Min Fu (Taichung, TW); Chi-Ching Ho (Taichung, TW); Cheng-Yu Kang (Taichung, TW); Yu-Po Wang (Taichung, TW)
Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
H01L23/49822H01L21/4857H01L21/486H01L23/367H01L23/49816H01L23/49833H01L23/49838H01L24/73H01L2224/73204H01L2924/3511
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Quick Facts
Patent No.
US 12,412,819
App. No.
18/643,424
Granted
Sep 9, 2025
Kind
B2
Abstract

Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.

Claims (15)

1. A method for manufacturing an electronic package, comprising:

providing a circuit structure including a plurality of auxiliary circuit layers and a package substrate having a plurality of main circuit layers, wherein the circuit structure has a first surface and a second surface opposite to each other, and a number of layers of the plurality of auxiliary circuit layers is used to replace a layer number configuration of the plurality of main circuit layers such that a number of layers of the plurality of main circuit layers is less than an original expected number of layers of the plurality of main circuit layers;

disposing an electronic component on the first surface of the circuit structure and electrically connecting the electronic component with the plurality of auxiliary circuit layers, wherein the circuit structure extends out of sides of the electronic component;

forming an encapsulant on the first surface of the circuit structure to encapsulate the electronic component to obtain a package module;

disposing the second surface of the circuit structure of the package module on the package substrate having the plurality of main circuit layers via a plurality of conductive components, wherein the plurality of main circuit layers are electrically connected to the plurality of auxiliary circuit layers via the plurality of conductive components; and

forming a packaging material on the package substrate, wherein the packaging material covers the plurality of conductive components,

wherein the plurality of auxiliary circuit layers have a single layer replacing 2 to 4 layers of the plurality of main circuit layers, and the original expected number of layers of the plurality of main circuit layers is at least sixteen.

2. The method of claim 1 , wherein the circuit structure has a vertical projected area smaller than a vertical projection area of the package substrate.

3. The method of claim 1 , wherein the package substrate includes a core layer and build-up structures disposed on opposite sides of the core layer, and each of the build-up structures includes a plurality of dielectric layers and the plurality of main circuit layers bonded to the plurality of dielectric layers.

4. The method of claim 3 , wherein the number of layers of the plurality of main circuit layers of the package substrate is at least ten.

5. The method of claim 1 , wherein the package substrate has an area of at least 60×60 mm 2 .

6. The method of claim 1 , wherein the electronic component has a plurality of electrode pads electrically connected to the plurality of auxiliary circuit layers, and a distance between the electrode pads is less than or equal to 60 μm.

7. The method of claim 1 , wherein the plurality of auxiliary circuit layers of the circuit structure facing a side of the package substrate have a plurality of electrical contact pads, and a distance between the electrical contact pads is 200 μm to 300 μm or 80 μm to 150 μm.

8. The method of claim 1 , further comprising disposing a plurality of ball pads on another side of the package substrate opposite to the package module, wherein a distance between the ball pads is 500 μm to 1,000 μm.

9. The method of claim 1 , further comprising disposing a heat sink on the package substrate for heat dissipation of the package module.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2024
From: FU, YI-MIN; HO, CHI-CHING; KANG, CHENG-YU; WANG, YU-PO
To: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Reel/Frame 067316/0576 →
Priority Claims (1)
TW 110138003 · Oct 13, 2021 · national
Continuity (2)
Division 17527434 · Nov 16, 2021
Related Publication 20240274519A1 · Aug 15, 2024
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