Methods for forming multi-gate transistors
View Patent ↗A semiconductor device includes a substrate, two source/drain features disposed on the substrate, a stack of channel layers disposed over the substrate and between the two source/drain features, and a gate structure disposed over and wrapping around the stack of channel layers. Each channel layer of the stack of channel layers has a dog-bone shape in a cross-sectional view including the two source/drain features and the stack of channel layers. The gate structure includes a seam.
1. A semiconductor device, comprising:
a substrate;
two source/drain features disposed on the substrate;
a stack of channel layers disposed over the substrate and between the two source/drain features; and
a gate structure disposed over and wrapping around the stack of channel layers,
wherein at least one channel layer of the stack of channel layers has a dog-bone shape in a cross-sectional view including the two source/drain features and the stack of channel layers,
wherein the dog-bone shape has top surfaces declining from the gate structure toward the two source/drain features, and
wherein the gate structure comprises a seam.
2. The semiconductor device of claim 1 ,
wherein the gate structure comprises an inner portion interleaving with the stack of channel layers and an outer portion disposed over the inner portion and the stack of channel layers,
wherein a composition of the inner portion is different from a composition of the outer portion.
3. The semiconductor device of claim 2 , wherein the inner portion comprises the seam.
4. The semiconductor device of claim 2 , wherein the inner portion has a substantially rounded rectangular shape, a substantially racetrack shape, or a substantially oval shape in the cross-sectional view.
5. The semiconductor device of claim 1 , wherein a bottom surface of the gate structure is below a top surface of the substrate.
6. The semiconductor device of claim 1 , further comprising an inner spacer feature disposed between two adjacent channel layers of the stack of channel layers and between the gate structure and one of the two source/drain features.
7. The semiconductor device of claim 6 , wherein an interface of the inner spacer feature and one of the two adjacent channel layer of the stack of channel layers is tilted and intersects the gate structure,
wherein the inner spacer has a vertical thickness increasing from the gate structure toward the one of the two source/drain features.
8. The semiconductor device of claim 6 , wherein a top surface and a bottom surface of the inner spacer feature are concave.
9. The semiconductor device of claim 1 , further comprising a gate spacer disposed on a sidewall of the gate structure and on a top surface of a topmost channel layer of the stack of channel layers,
wherein the gate structure and the topmost channel layer of the stack of channel layers has a tilted interface.
10. A semiconductor device, comprising:
a first source/drain feature and a second source/drain feature;
a channel member disposed between the first source/drain feature and the second source/drain feature, wherein the channel member comprises a first connection portion contacting the first source/drain feature, a second connection portion contacting the second source/drain feature, and a channel portion extending between the first connection portion and the second connection portion, wherein a thickness of the first connection portion is greater than a thickness of the channel portion;
an inner spacer feature disposed below a tilted bottom surface of the first connection portion; and
a gate structure disposed over and wrapping around the channel member,
wherein the tilted bottom surface of the first connection portion declines from the first source/drain feature toward the gate structure.
11. The semiconductor device of claim 10 ,
wherein the gate structure comprises an inner portion wrapping around the channel member and an outer portion disposed over the inner portion and the channel member,
wherein the inner portion comprises a gate dielectric material wrapping around the channel member, and a first work function material over and wrapping around the gate dielectric material, and
wherein the outer portion comprises the gate dielectric material, the first work function material over the gate dielectric material, a second work function material over the first work function material, and a metal fill material over the second work function material.
12. The semiconductor device of claim 11 , wherein the inner portion has a substantially rounded rectangular shape or a substantially racetrack shape in a cross-sectional view including the first source/drain feature, the second source/drain feature, the channel member, and the gate structure.
13. The semiconductor device of claim 11 , wherein the inner portion further comprises a void surrounded by the first work function material.
14. The semiconductor device of claim 10 , further comprising a substrate,
wherein the first source/drain feature and the second source/drain feature are disposed on the substrate, and
wherein the gate structure extends into the substrate.
15. The semiconductor device of claim 10 , further comprising a gate spacer disposed on a sidewall of a portion of the gate structure and a top surface of the first connection portion,
wherein the portion of the gate structure and the first connection portion have a tilted interface.
16. The semiconductor device of claim 10 ,
wherein a top surface of the first connection portion declines from the gate structure toward the first source/drain feature.
17. A semiconductor device, comprising:
a substrate;
a source feature and a drain feature disposed over the substrate;
a channel member disposed between the source feature and the drain feature, wherein the channel member comprises a first connection portion contacting the source feature, a second connection portion contacting the drain feature, and a channel portion extending between the first connection portion and the second connection portion, wherein a thickness of the first connection portion is greater than a thickness of the channel portion;
a first inner spacer feature disposed on a top surface of the first connection portion;
a second inner spacer feature landing on a bottom surface of the first connection portion; and
a gate structure wrapping around the channel portion of the channel member,
wherein the first connection portion of the channel member interfaces the gate structure,
wherein a ratio of a thickness of the first inner spacer feature to a width of the first inner spacer feature is between about 0.9 and about 1.2, and
wherein a portion of the gate structure extends into the substrate.
18. The semiconductor device of claim 17 ,
wherein the gate structure comprises an inner portion disposed between the source feature and the drain feature and an outer portion disposed over the source feature and the drain feature,
wherein a composition of the inner portion is different from a composition of the outer portion,
wherein the first connection portion of the channel member is disposed on the inner portion of the gate structure, and
wherein the bottom surface of the first connection portion declines from the source feature toward the inner portion of the gate structure.
19. The semiconductor device of claim 18 ,
wherein the inner portion comprises a first gate dielectric layer wrapping around the channel member, and a first work function layer over the first gate dielectric layer, and
wherein the outer portion comprises a second gate dielectric layer, a second work function layer over the second gate dielectric layer, a third work function layer over the second work function layer, and a metal fill layer over the third work function layer.
20. The semiconductor device of claim 19 ,
wherein the inner portion further comprises a seam enclosed in the first work function layer.