IP Library Granted Patent US 12,302,607
Granted Patent B2
US 12,302,607 · App. 18/670,132 · Granted May 13, 2025

Backside gate contact

Inventors: Huan-Chieh Su (Changua County, TW); Chun-Yuan Chen (HsinChu, TW); Lo-Heng Chang (Hsinchu, TW); Li-Zhen Yu (New Taipei, TW); Lin-Yu Huang (Hsinchu, TW); Cheng-Chi Chuang (New Taipei, TW); Chih-Hao Wang (Hsinchu County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10D30/6735H10D30/6757
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Quick Facts
Patent No.
US 12,302,607
App. No.
18/670,132
Granted
May 13, 2025
Kind
B2
Abstract

Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to one embodiment includes first nanostructures, a first gate structure wrapping around each of the first nanostructures and disposed over an isolation structure, and a backside gate contact disposed below the first nanostructures and adjacent to the isolation structure. A bottom surface of the first gate structure is in direct contact with the backside gate contact.

Claims (45)

1. A semiconductor structure, comprising:

a first plurality of nanostructures disposed over a backside dielectric layer;

a first gate structure wrapping around each of the first plurality of nanostructures;

a second plurality of nanostructures disposed over a backside gate contact;

a second gate structure wrapping around each of the second plurality of nanostructures; and

an isolation structure disposed between the backside dielectric layer and the backside gate contact along a first direction,

wherein the backside gate contact is spaced apart from the isolation structure by a liner.

2. The semiconductor structure of claim 1 , wherein a portion of the first gate structure and a portion of the second gate structure are disposed over the isolation structure.

3. The semiconductor structure of claim 1 , further comprising a dielectric fin disposed over the isolation structure and extending along a second direction perpendicular to the first direction.

4. The semiconductor structure of claim 3 , wherein the dielectric fin is sandwiched between the first gate structure and the second gate structure along the first direction.

5. The semiconductor structure of claim 3 , further comprising:

a gate cut feature disposed on the dielectric fin,

wherein the gate cut feature is sandwiched between the first gate structure and the second gate structure along the first direction.

6. The semiconductor structure of claim 1 , wherein the first plurality of nanostructures extend along a second direction perpendicular to the first direction toward a source/drain feature.

7. The semiconductor structure of claim 6 , further comprising a dielectric plug disposed below the source/drain feature.

8. The semiconductor structure of claim 7 , wherein the liner extends between the dielectric plug and the backside gate contact.

9. The semiconductor structure of claim 7 , wherein the liner comprises silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride.

10. A semiconductor structure, comprising:

an isolation structure disposed between a dielectric plug and a backside gate contact along a direction;

a first gate structure disposed over the dielectric plug and a first portion of the isolation structure;

a second gate structure disposed over the backside gate contact and a second portion of the isolation structure; and

a dielectric fin disposed over the isolation structure and sandwiched between the first gate structure and the second gate structure,

wherein the backside gate contact partially extends into a bottom surface of the second gate structure.

11. The semiconductor structure of claim 10 , wherein the backside gate contact is spaced apart from the isolation structure by a liner.

12. The semiconductor structure of claim 11 , wherein the liner comprises silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride.

13. The semiconductor structure of claim 11 , wherein the liner comprises a thickness between about 0.5 nm and about 5 nm.

14. The semiconductor structure of claim 10 , further comprising:

a gate cut feature disposed on the dielectric fin,

wherein the gate cut feature is sandwiched between the first gate structure and the second gate structure.

15. The semiconductor structure of claim 14 , further comprising:

a self-aligned capping layer disposed over top surfaces of the gate cut feature, the first gate structure and the second gate structure.

16. The semiconductor structure of claim 15 , wherein the gate cut feature comprises silicon oxide, silicon nitride, silicon oxynitride.

17. A semiconductor structure, comprising:

an isolation structure;

a dielectric fin disposed over the isolation structure;

a gate cut feature disposed over the dielectric fin;

a first gate structure partially disposed over the isolation structure;

a second gate structure partially disposed over the isolation structure and spaced apart from the first gate structure by the dielectric fin and the gate cut feature; and

a backside gate contact extending along a first sidewall of the isolation structure and extending toward the second gate structure.

18. The semiconductor structure of claim 17 ,

wherein the backside gate contact is spaced apart from a sidewall of the isolation structure by a liner,

wherein the liner comprises silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride.

19. The semiconductor structure of claim 17 , further comprising:

a dielectric plug extending along a second sidewall of the isolation structure toward the first gate structure.

20. The semiconductor structure of claim 17 , wherein the backside gate contact partially extends into the second gate structure.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE NAME OF THE 3RD INVENTOR PREVIOUSLY RECORDED AT REEL: 67481 FRAME: 419. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 11, 2024
From: SU, HUAN-CHIEH; CHEN, CHUN-YUAN; YU, LI-ZHEN; HUANG, LIN-YU; CHANG, LO-HENG; CHUANG, CHENG-CHI; WANG, CHIH-HAO
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 067698/0205 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 21, 2024
From: SU, HUAN-CHIEH; CHUN, CHUN-YUAN; YU, LI-ZHEN; HUANG, LIN-YU; CHANG, LO-HENG; CHUANG, CHENG-CHI; WANG, CHIH-HAO
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 067481/0419 →
Continuity (4)
Continuation 18321620 · May 22, 2023
Continuation 17228955 · Apr 13, 2021
Provisional Application 63151228 · Feb 19, 2021
Related Publication 20240304695A1 · Sep 12, 2024
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